Table of Contents
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Table 38.
Arithmetic and Logical Instructions (8-bit) (Continued)
Operation
Name
Mnemonics
Op Code
SUBC
SBC A,g
10 011 g
SBC A,(HL)
10 011 110
SBC A,m
11 011 110 S
<m>
SBC A,(IX + d) 11 011 101
10 011 110
<d>
SBC A,(IY + d) 11 111 101
10 011 110
<d>
TEST
TST g**
11 101 101
00 g 100
TST {HL)**
11101101
00 110 100
TST m**
11 101 101 S
01 100 100
<m>
XOR
XOR g
10 101 g
XOR (HL)
10 101 110
XOR m
11 101 110 S
<m>
XOR (IX + d)
11 011 101
10 101 110
<d>
Addressing
Immed Ext Ind
Reg RegI Imp Rel
S
D
S
D
D
S
D
S
D
S
S
S
D
S
D
D
S
D
Family MPU User Manual
Bytes States Operation
1
4
Ar-gr-c→Ar
1
6
Ar-(HL)
-c→Ar
M
2
6
Ar-m-c→Ar
3
14
Ar-(IX + d)
-c→Ar
M
3
14
Ar-(IY + d)
-c→Ar
M
2
7
Ar•gr
2
10
Ar•(HL)
M
3
9
Ar•m
1
4
Ar
+ gr→Ar
⊕
1
6
Ar
+ (HL)
→Ar
⊕
M
2
6
Ar
⊕
+ m→Ar
)
3
14
→Ar
Ar⊕ + (IX + d)
M
UM005004-0918
Z8018x
215
Flags
7
6
4
2
1
0
S Z
H P/V N C
↑ ↑ ↑ V
S ↑
↑ ↑ ↑ V
S ↑
↑ ↑ ↑ V
S ↑
↑ ↑ ↑ V
S ↑
↑ ↑ ↑ V
S ↑
↑ ↑ S P
R R
↑ ↑ S P
R R
↑ ↑ S P
R R
↑ ↑ R P
R R
↑ ↑ R P
R R
↑ ↑ R P
R R
↑ ↑ R P
R R
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