Table of Contents
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List of Tables
Z80180, Z8S180, Z8L180 MPU Operation . . . . . . . . . . . . . . . . . . . .1
Table 9.
Status Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Multiplexed Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . .12
Memory Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Wait State Insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
(Z8S180/Z8L180-Class Processor Only) . . . . . . . . . . . . . .37
I/O Address Map for Z80180-Class Processors Only . . . . .44
(Z8S180/Z8L180-Class Processors Only) . . . . . . . . . . . . .48
State of IEF1 and IEF2. . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
Vector Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
RETI Control Signal States . . . . . . . . . . . . . . . . . . . . . . . . .85
DRAM Refresh Intervals . . . . . . . . . . . . . . . . . . . . . . . . . .89
Channel 0 Destination . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98
Channel 0 Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99
Transfer Mode Combinations . . . . . . . . . . . . . . . . . . . . . . .99
Channel 1 Transfer Mode . . . . . . . . . . . . . . . . . . . . . . . . .102
DMA Transfer Request . . . . . . . . . . . . . . . . . . . . . . . . . . .110
Data Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131
Divide Ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134
ASCI Baud Rate Selection . . . . . . . . . . . . . . . . . . . . . . . . .142
Clock Mode Bit Values . . . . . . . . . . . . . . . . . . . . . . . . . . .144
2^ss Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .145
CSI/O Baud Rate Selection . . . . . . . . . . . . . . . . . . . . . . . .150
Family MPU User Manual
UM005004-0918
Z8018x
xii
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Do you have a question about the Z8018 Series and is the answer not in the manual?
Questions and answers
are there a timing diagrams for PUSH and POP instructions?
The timing diagrams for the PUSH and POP instructions for the ZiLOG Z8018 Series are as follows:
POP Instruction (e.g., POP IX or POP IY):
- Machine Cycle 1 (MC1): Fetch POP opcode.
- Machine Cycle 2 (MC2): Fetch address code.
- Machine Cycle 3 (MC3): Read from memory at SP (Stack Pointer); data goes to low byte (e.g., IXL or IYL).
- Machine Cycle 4 (MC4): Read from memory at SP+1; data goes to high byte (e.g., IXH or IYH).
PUSH Instruction (e.g., PUSH IX or PUSH IY):
- Machine Cycle 1 (MC1): Fetch PUSH opcode.
- Machine Cycle 2 (MC2): Fetch address code.
- Machine Cycle 3 (MC3): Decrement SP by 1 and write high byte (e.g., IXH or IYH) to memory at SP.
- Machine Cycle 4 (MC4): Decrement SP by 1 and write low byte (e.g., IXL or IYL) to memory at SP.
Each machine cycle includes three T-states (T1, T2, T3), and memory control signals (such as MREQ, RD, WR) are active as needed during these cycles.
This answer is automatically generated