ZiLOG Z8018 Series User Manual page 36

Z8018x
Family MPU User Manual
22
T1
Phi
–
A0 A19
–
D0 D7
WAIT
MREQ
RD
WR
UM005004-0918
Read Cycle
T2 TW
Figure 12. Memory Read/Write (with Wait State) Timing Diagram
I/O Read/Write Timing
I/O Read/Write operations differ from memory Read/Write operations in
the following three ways:
•
The IORQ (I/O Request) signal is asserted Low instead of the MREQ
signal
•
The 16-bit I/O address is not translated by the MMU
•
A16–A19 are held Low
At least one Wait State (TW) is always inserted for I/O read and write
cycles (except internal I/O cycles).
Figure 13 illustrates I/O read/write timing with the automatically inserted
Wait State (TW).
T3 T1
Read data
Write Cycle
T2 TW T3
Write data