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ZiLOG eZ80F91 User Manual

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eZ80F91 Development Kit
User Manual
PRELIMINARY
UM014210-1003
ZiLOG Worldwide Headquarters • 532 Race Street • San Jose, CA 95126
Telephone: 408.558.8500 • Fax: 408.558.8300 •
www.ZiLOG.com

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  • Page 1 Development Kit User Manual PRELIMINARY UM014210-1003 ZiLOG Worldwide Headquarters • 532 Race Street • San Jose, CA 95126 Telephone: 408.558.8500 • Fax: 408.558.8300 • www.ZiLOG.com...
  • Page 2 Document Disclaimer ZiLOG is a registered trademark of ZiLOG Inc. in the United States and in other countries. All other products and/or service names mentioned herein may be trademarks of the companies with which they are associated. ©2003 by ZiLOG, Inc. All rights reserved. Information in this publication concerning the devices, applications, or technology described is intended to suggest possible uses and may be superseded.

  • Page 3: Safeguards

    Development Kit User Manual Safeguards The following precautions must be observed when working with the devices described in this document. Caution: Always use a grounding strap to prevent damage resulting from electrostatic discharge (ESD). UM014210-1003 PRELIMINARY Safeguards...
  • Page 4 Development Kit User Manual PRELIMINARY UM014210-1003...

  • Page 5: Table Of Contents

    Operational Description ........10 eZ80F91 Module Interface ....... 10 Application Module Interface .
  • Page 6 Module ........

  • Page 7: List Of Figures

    Development Platform and eZ80F91 Module ....... . 32 Figure 11. Possible Bus Contention without Fast Buffer ..45 Figure 12.
  • Page 8 Miscellaneous ....... 66 Figure 24. eZ80F91 Module Schematic Diagram, #2 of 3—CPU and PHY .

  • Page 9: List Of Tables

    JP21 ......... . 18 Table 4. Jumper, eZ80F91 Module ......21 Table 5.
  • Page 10 Development Kit User Manual Table 26. J20—EX_FL_DIS ....... 41 Table 27.

  • Page 11: Introduction

    Introduction The eZ80F91 Development Kit provides a general-purpose platform for evaluating the capabilities and operation of ZiLOG’s eZ80F91 microcon- troller. The eZ80F91 is a member of ZiLOG’s eZ80Acclaim! product family, which offers on-chip Flash capability. The eZ80F91 Development ® Kit features two primary boards: the eZ80 Development Platform and the eZ80F91 Module.

  • Page 12: Hardware Specifications

    – Telephone jack • eZ80F91 Module: – eZ80F91 device operating at 50 MHz, with 256 KB of internal Flash memory and 8 KB of internal SRAM memory – 512 KB of off-chip SRAM memory – 1 MB of off-chip Flash memory (footprint) –...

  • Page 13: Ez80F91 Development Kit Overview

    Development Kit Overview The purpose of the eZ80F91 Development Kit is to provide the developer with a set of tools for evaluating the features of the eZ80F91 microcon- troller and to be able to develop a new application before building appli- cation hardware.

  • Page 14: Figure 1. Ez80 ® Development Platform Block Diagram With Ez80F91

    RS485_0/1 Connect SRAM (512 KB) (7x5 matrix) Embedded Modem GPIO IrDA Transceiver EEPROM Address Decoder Register External Battery eZ80F91 Module Application Module Headers ® Figure 1. eZ80 Development Platform Block Diagram with eZ80F91 Module eZ80F91 Development Kit Overview PRELIMINARY UM014210-1003...
  • Page 15 figure. Note: Key to blocks A–E. A. Power and serial communications. D. Application module interfaces. B. eZ80F91 Module interface. E. GPIO and LED with Address Decoder. C. JTAG and ZDI debug interfaces. ®...

  • Page 16: Figure 3. The Ez80F91 Module

    Development Kit User Manual Figure 3 is a photographic representation of the eZ80F91 Module seg- mented into its key blocks, as shown in the legend for the figure. Note: Key to blocks A–C. A. eZ80F91 Module interfaces. B. eZ80F91 CPU.

  • Page 17: Ez80 ® Development Platform

    ® The eZ80 Development Platform consists of seven major hardware blocks. These blocks, listed below, are diagrammed in Figure 4. • eZ80F91 Module interface (2 female headers) • ® Power supply for the eZ80 Development Platform, the eZ80F91 Module, and application modules •...

  • Page 18: Figure 4. Basic Ez80

    Development Kit User Manual GPIO Address Bus ® eZ80 Module Interface Data Bus RS232-0 SRAM (Console) (512 KB up to 2 MB) RS232-1 (Modem) RS485_0/1 Connect (7x5 matrix) Embedded Modem GPIO Address EEPROM Decoder Register Application Module Headers ®...

  • Page 19: Physical Dimensions

    Development Kit User Manual Physical Dimensions ® The dimensions of the eZ80 Development Platform PCB is 177.8 mm x 182.9 mm. The overall height is 38.1 mm. See Figure 5. 175.3 mm 114.3 mm 43.2 mm 96.5 mm 55.9 mm 157.5 mm...

  • Page 20: Operational Description

    F91_WE • RTC_V A description of these five signals follows. 1. These input signals are only used if external Flash memory is present on the eZ80F91 Module. As shipped from the factory, external Flash is not installed. Operational Description PRELIMINARY...
  • Page 21 Development Platform. When the F91_WE signal is active Low, internal Flash on the F91_WE. eZ80F91 Module is enabled for writing. This signal is inverted from the WP signal of on the eZ80F91 Module. RTC_V is a test point for the Real Time Clock power sup- RTC_V ply.

  • Page 22: Figure 6. Ez80 ® Development Platform Peripheral Bus Connector Pin Configuration-Jp1

    Development Kit User Manual Peripheral Bus Connector Figure 6 illustrates the pin layout of the Peripheral Bus Connector in the ® 50-pin header, located at position JP1 on the eZ80 Development Plat- form. Table 2 identifies the pins and their functions.

  • Page 23: Table 2. Ez80 ® Development Platform Peripheral Bus Connector

    66 through 2. The Power and Ground nets are connected directly to the eZ80F91 device. 3. Additional note: external capacitive loads on RD, WR, IORQ, MREQ, D0–D7 and A0–A23 should be below 10 pF to satisfy the timing requirements for the eZ80 CPU. All unused inputs...
  • Page 24 66 through 2. The Power and Ground nets are connected directly to the eZ80F91 device. 3. Additional note: external capacitive loads on RD, WR, IORQ, MREQ, D0–D7 and A0–A23 should be below 10 pF to satisfy the timing requirements for the eZ80 CPU. All unused inputs...
  • Page 25 66 through 2. The Power and Ground nets are connected directly to the eZ80F91 device. 3. Additional note: external capacitive loads on RD, WR, IORQ, MREQ, D0–D7 and A0–A23 should be below 10 pF to satisfy the timing requirements for the eZ80 CPU. All unused inputs...
  • Page 26 66 through 2. The Power and Ground nets are connected directly to the eZ80F91 device. 3. Additional note: external capacitive loads on RD, WR, IORQ, MREQ, D0–D7 and A0–A23 should be below 10 pF to satisfy the timing requirements for the eZ80 CPU. All unused inputs...

  • Page 27: Figure 7. Ez80 ® Development Platform I/O Connector Pin Configuration-Jp2

    Development Kit User Manual I/O Connector Figure 7 illustrates the pin layout of the I/O Connector in the 50-pin ® header, located at position JP2 on the eZ80 Development Platform. Table 3 identifies the pins and their functions. GND_EXT...
  • Page 28 1. For the sake of simplicity in describing the interface, Power and Ground nets are omitted from this table. The entire interface is represented in the eZ80F91 Module Schematics on pages 66 through 2. The Power and Ground nets are connected directly to the eZ80F91 device. Operational Description PRELIMINARY UM014210-1003...
  • Page 29 1. For the sake of simplicity in describing the interface, Power and Ground nets are omitted from this table. The entire interface is represented in the eZ80F91 Module Schematics on pages 66 through 2. The Power and Ground nets are connected directly to the eZ80F91 device. ® UM014210-1003 PRELIMINARY...
  • Page 30 1. For the sake of simplicity in describing the interface, Power and Ground nets are omitted from this table. The entire interface is represented in the eZ80F91 Module Schematics on pages 66 through 2. The Power and Ground nets are connected directly to the eZ80F91 device. Operational Description PRELIMINARY UM014210-1003...

  • Page 31: Table 4. Jumper, Ez80F91 Module

    To program internal on-chip Flash memory, the JP3 shunt must be installed. Table 4 lists the setting for the JP3 jumper that is resident on the eZ80F91 Module. A sample project provided with ZDS II, Led- , can only be programmed into on-chip Flash memory.

  • Page 32: Application Module Interface

    Implementing an application module with the Application Module ® Interface requires that the eZ80F91 Module also be mounted on the eZ80 Development Platform, because the eZ80F91 device controls the applica- tion. To mount an application module, use the two male headers J6 and J8.
  • Page 33 Development Kit User Manual Table 5. GPIO Connector J6* (Continued) Signal Pin # Function Direction Notes Chip Select 3 of This signal is also present on the CPU the J8. EM_D[7:1] 21,23,25, Emulated, Bit IN/OUT 27,29,31, [7:1] Reserved PC[7:0]...

  • Page 34: I/O Functionality

    Development Kit User Manual Table 6. CPU Bus Connector J8* Signal Pin # Function Direction A[0:7] 3–10 Address Bus, Low Byte A[8:15] 13–20 Address Bus, High Byte A[16:23] 23–30 Address Bus, Upper Byte READ Signal RESET Push Button Reset...

  • Page 35: Table 7. Led And Port Emulation Addresses

    Development Kit User Manual Table 7 lists the addresses of registers that allow access to the above func- tions. The register at address controls GPIO Output Control and 800000h LED Anode register functions. The register at address controls 800001h the register functions for the LED cathode, modem reset, and user triggers.

  • Page 36: Table 9. Gpio Data Register

    Development Kit User Manual The GPIO Data Register receives inputs or provides outputs for each of the seven GPIO lines, depending on the configuration of the port. See Table 9. Table 9. GPIO Data Register Function/Bit # GPIO D0...

  • Page 37: Embedded Modem Socket Interface

    Development Kit User Manual Ground Trigger output Trig2 Trig1 Figure 8. Trigger Pins J21 and J22 Bits 6 and 7 in Table 14 are the control bits for the user triggers. If either bit is a 1, the corresponding Trig1 and Trig2 signals are driven High. If either bit is 0, the corresponding Trig1 and Trig2 signals are driven Low.

  • Page 38: Figure 9. Embedded Modem Socket Interface-J1, J5, And J9

    Development Kit User Manual Figure 9. Embedded Modem Socket Interface—J1, J5, and J9 Table 10. Connector J5 Pin Symbol Description M-TIP Telephone Line Interface—TIP. M-RING Telephone Line Interface—RING. Table 11. Connector J9 Pin Symbol Description MRESET Reset, active Low, 50–100 ms. Closure to GND for reset.

  • Page 39: Table 12. Connector J1

    Development Kit User Manual Table 11. Connector J9 DCD indicator; can drive an LED anode without additional circuitry. RxD indicator; can drive an LED anode without additional circuitry. DTR indicator; can drive an LED anode without additional circuitry. TxD indicator; can drive an LED anode without additional circuitry.

  • Page 40: Ez80 ® Development Platform Memory

    Development Kit User Manual The tested modem for this eZ80F91 Development Kit is a MultiTech Sys- tems (formerly Conexant) socket modem, part number SC56H1. Either the 3.3 V or the 5.0 V version of the modem can be used. However, jumper J12 should be configured accordingly—see Table 19.
  • Page 41 Product Specification (PS0192) for more information. Flash Memory The eZ80F91 Development Kit allows off-chip Flash memories between 1 MB and 4 MB. This Flash memory is entirely located on the eZ80F91 Module (as footprint only; as shipped from the factory, external Flash is not installed).

  • Page 42: Figure 10. Memory Map Of The Ez80

    120000h Flash memory 11FFFFh on the module Up to 4 MB Flash Memory 1 MB 040000h 03FFFFh On-chip 256 KB Flash memory 000000h ® Figure 10. Memory Map of the eZ80 Development Platform and eZ80F91 Module Operational Description PRELIMINARY UM014210-1003...

  • Page 43: Leds

    Development Kit User Manual As seen in the memory map in Figure 10, Chip Selects and Wait States. Flash memory is enabled by CS0, on-module SRAM is enabled by CS1, and the remainder of the resources are enabled by CS2. The number of wait states (N) for each Chip Select are indicated in Table 13.

  • Page 44: Table 14. Bit Access To The Led Cathode, Modem, And Triggers

    Modem RST Trig 1 Trig 2 An LED display sample program is shipped with the eZ80F91 Develop- ment Kit. Please refer to the eZ80Acclaim!™ Development Kits Quick Start Guide (QS0020) or to the Tutorial section in the ZiLOG Developer Studio—eZ80Acclaim! User Manual (UM0144).

  • Page 45: Push Buttons

    The eZ80 Development Platform provides user controls in the form of push buttons. These push buttons serve as input devices to the eZ80F91 device. The programmer can use them as necessary for application devel- opment. All push buttons are connected to the GPIO Port B pins.

  • Page 46: Jumpers

    UART0 is configured to work with the RS232 or the Module disabled RS485 interfaces. IrDA on eZ80F91 IrDA is enabled to work with UART0 on the eZ80F91 Module enabled device. Jumper J3 The J3 jumper connection controls GPIO emulation mode and communi- cation with the 7 x 5 LED.

  • Page 47: Table 17. J7-Flashwe (Off-Chip)

    See Table 17. Table 17. J7—FlashWE (Off-Chip)* Shunt Status Function Affected Device The Flash boot sector of the eZ80F91 Flash boot sector of the eZ80F91 Module is write-protected. Module. The Flash boot sector of the eZ80F91 Flash boot sector of the eZ80F91 Module is enabled for writing or Module.

  • Page 48: Table 19. J12-5Vdc/3.3Vdc For An Embedded Modem

    Development Kit User Manual Jumper J12 The J12 jumper connection controls the selection of a 5 V or 3 VDC power supply to the embedded modem, if an embedded modem is used. See Table 19. Table 19. J12—5VDC/3.3VDC for an Embedded Modem...

  • Page 49: Table 21. J15-Rs485_1_En

    Development Kit User Manual Jumper J15 The J15 jumper connection controls the selection RS485 circuit along with UART0. When the shunt is placed, the RS485 circuit is enabled. See ® Table 21. RS485 functionality will be available in future eZ80 devices.

  • Page 50: Table 23. J17-Rt_1

    Development Kit User Manual Jumper J17 The J17 jumper connection controls the selection of the RS485 termina- tion resistor circuit. When the shunt is placed, the RS485 termination resistor circuit is enabled. See Table 23. Table 23. J17—RT_1* Shunt...

  • Page 51: Table 25. J19-Ex_Sel

    Development Kit User Manual Jumper J19 The J19 jumper connection selects the range of memory addresses for the external chip select signal, CS_EX, to the application module. See Table 25. Table 25. J19—EX_SEL Shunt Status Function Affected Device 1–2...

  • Page 52: Connectors

    EEPROM and the U13 Configuration register. The EEPROM provides 16 KB of memory. The Configuration register provides access to control the configuration of an application-specific function at the Application Module Interface. Neither device is utilized by the eZ80F91 Development I2C Devices PRELIMINARY...
  • Page 53 Development Kit User Manual Kit software. The user is free to develop proprietary software for these two devices. The addresses for accessing these devices are listed in Table 27. Table 27. I C Addresses Device/Bit # EEPROM (U10)* Configuration Register (U13) Note: *EEPROM address bits A0 and A1 are configured for 0s.

  • Page 54: Ez80F91 Module

    Despite its small footprint, the eZ80F91 Module provides a CPU, Flash memory, Ethernet interface, SRAM, an IrDA transceiver, and a real-time clock with a back-up battery. This module is powered by the eZ80F91 ® microcontroller, a new member of ZILOG’s eZ80 product family.

  • Page 55: Figure 11. Possible Bus Contention Without Fast Buffer

    8.8 ns + 25 ns = 33.8 ns can transpire before Flash memory stops driving the data bus. At that time, the eZ80F91 device is well into the next bus cycle. Assuming this next cycle is the Memory Write cycle, then the data output of the eZ80F91 device is valid not later than T3 = 7.5 ns, and the write pulse is asserted not later than 4.5 ns after the...
  • Page 56 As of the date of publication of this document, ZiLOG has not completed an analysis of the effect that this 6.8 ns period of bus contention has on the design.

  • Page 57: Physical Dimensions

    Development Kit User Manual Physical Dimensions The footprint of the eZ80F91 Module PCB is 63.5 mm x 78.7 cm. With an RJ-45 Ethernet connector, the overall height is 25 mm. See Figure 12. 16.5 mm 56.0 mm eZ80F91 MODULE 78.7 mm...

  • Page 58: Figure 13. Ez80F91 Module-Top Layer

    Development Kit User Manual Figure 13 illustrates the top layer silkscreen of the eZ80F91 Module. eZ80F91 MODULE Figure 13. eZ80F91 Module—Top Layer Functional Description PRELIMINARY UM014210-1003...

  • Page 59: Figure 14. Ez80F91 Module-Bottom Layer

    Development Kit User Manual Figure 14 illustrates the bottom layer silkscreen of the eZ80F91 Module. DJP 2002 MADE IN U.S.A. ZiLOG FAB: 98C0879-001 REV A Figure 14. eZ80F91 Module—Bottom Layer UM014210-1003 PRELIMINARY eZ80F91 Module...

  • Page 60: Operational Description

    User Manual Operational Description The purpose of the eZ80F91 Module as a feature of the eZ80F91 Devel- opment Kit is to provide the application developer with a plug-in tool to evaluate such features of the eZ80F91 device as on-chip EMAC, SRAM, Flash, etc.

  • Page 61: Reset Generator

    When the IrDA function is enabled, the final output to the RxD and TxD pins are routed through the 3/16 pulse generator. Another signal that is used in the eZ80F91 Module’s IrDA system is Shut_Down (SD). The SD pin is connected to PD2 on the eZ80F91 Mod- UM014210-1003 PRELIMINARY...

  • Page 62: Figure 15. Irda Hardware Connections

    IrDA transceiver. The SD pin must be set Low to enable the IrDA transceiver. On the eZ80F91 Module, a two-input OR gate is used to allow an external pin to shut down the IrDA transceiver.

  • Page 63: Flash Loader Utility

    //Output a byte to the uart0 port. Flash Loader Utility The Flash Loader utility integrated within ZDS II allows the user a conve- nient way to program on-chip Flash memory. Please refer to the ZiLOG Developer Studio—eZ80Acclaim! User Manual (UM0144) for more details.

  • Page 64: Changing The Power Supply Plug

    Development Kit User Manual Pin 60 of the eZ80F91 Module’s JP1 connector must align with the pin 50 ® socket on the eZ80 Development Platform’s JP1 connector; pin 60 of the ® eZ80F91 Module’s JP2 connector must align with pin 50 of the eZ80 Development Platform’s JP2 socket.

  • Page 65: Figure 17. Inserting A New Plug Configuration

    Development Kit User Manual 4. Push the new plug configuration down until it snaps into place, as indicated in Figure 17. Figure 17. Inserting a New Plug Configuration UM014210-1003 PRELIMINARY eZ80F91 Module...

  • Page 66: Zpak Ii

    JTAG will be supported in the next offering of eZ80 products. Application Modules ZiLOG offers the Thermostat Application module, which can be used for evaluating and developing process control and simple I/O applications. The Thermostat Application module is equipped with an LCD display that can be used to display process control and other physical parameters.

  • Page 67: Zds Ii

    ® development environment. Based on the Windows Win98SE/NT4.0- SP6/Win2000-SP2/WinXP user interfaces, ZDS II integrates a language- sensitive editor, project manager, C-Compiler, assembler, linker, librarian, and source-level symbolic debugger that supports the eZ80F91 device. UM014210-1003 PRELIMINARY ZDS II...
  • Page 68 Development Kit User Manual PRELIMINARY UM014210-1003...

  • Page 69: Troubleshooting

    Debug Reset + Go in ZDS. IrDA Port Not Working If you plan on using the IrDA transceiver on the eZ80F91 Module, make sure the hardware is set up as follows: • Jumper J2 must be OFF (to enable the control gate that drives the IrDA device) •...
  • Page 70 Development Kit User Manual Get the latest software updates from ZiLOG as soon as they are available! Contacting ZiLOG Customer Support PRELIMINARY UM014210-1003...

  • Page 71: Schematic Diagrams

    Development Kit User Manual Sc hematic Diagrams ® eZ80 Development Platform ® Figures 18 through 22 diagram the layout of the eZ80 De v elopment Platform . A[23:0] DO NOT USE J6_17 AND J6_35 A[23:0] MA10 MA13 9V_DC MA15...

  • Page 72: Figure 19. Ez80 ® Development Platform Schematic Diagram

    eZ80F9 1 D evelopment Kit User Manual R6 10K Ferrite Core A[23:0] M_TIP -CS2 -CS_EX_IN I/O0 -FL_DIS -MEM_CEN1 I/O1 -MEM_CEN1 -MEM_CEN2 -FL_DIS -CS0 I/O2 -MEM_CEN2 -MEM_CEN3 I/O3 -MEM_CEN3 -MEM_CEN4 I/O4 -MEM_CEN4 I/O5 -L_RD -EM_EN I/O6 I/O7 -DIS_FL SIDACTOR P3100SB RJ14 I/O8 I/O9 M_RING...
  • Page 73 eZ80F9 1 D evelopment Kit User Manual A[23:0] A[23:0] D[7:0] D[7:0] D[7:0] D[7:0] A[23:0] A[23:0] A[23:0] A[23:0] VDD0 VDD0 VDD0 VDD0 VDD1 VDD1 VDD1 VDD1 -MEM_CEN1 -MEM_CEN2 -MEM_CEN3 -MEM_CEN4 0.1uF 0.1uF 0.1uF 0.1uF VSS0 VSS0 VSS0 VSS0 VSS1 VSS1 VSS1 VSS1 D[7:0] D[7:0]...

  • Page 74: Figure 20. Ez80 ® Development Platform Schematic Diagram

    eZ80F9 1 D evelopment Kit User Manual 9VDC 9VDC 0.1uF LM7805C/TO220/0.5A RXE160 + C19 HEADER 5 22/10 0.1uF 0.1uF RESET TXD0 PD0_TXD0 T1IN T1OUT PWR JACK -RESET 22uF T2IN T2OUT RTS0 T3IN T3OUT PD2_RTS0 3.3V -CON_DIS FORCEOFF VIN VOUT FORCEON INVALID + C28 LT1086-3.3/TO220...

  • Page 75: Figure 22. Ez80 ® Development Platform Schematic Diagram

    eZ80F9 1 D evelopment Kit User Manual MATES WITH AMP = 749268-1 LENGTH = 5' WIRES 28 AWG ® Figure 22. eZ80 Development Platform Schematic Diagram, #5 of 5—RS-485 Cable UM014210-1003 PRELIMINARY Schematic Diagrams...

  • Page 76: Ez80F91 Module

    Module Figures 23 through 25 diagram the layout of the eZ80F91 Module . Ethernet circuiting de vices are not loaded on the eZ80F91 Module . Ho we v er , these de vices appear in the follo wing schematics for reference purposes.

  • Page 77: Figure 24. Ez80F91 Module Schematic Diagram, #2 Of 3-Cpu And

    0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF PD3_CTS0 PD2_RTS0 RTC_VDD PD1_RXD0_IRRXD RTC_XOUT PD0_TXD0_IRTXD RTC_XIN PD[0:7] -HALT_SLP HALT_SLP CLK_OUT -INSTRD INSTRD 12pF 12pF TRIGOUT TRIGOUT EZ80F91 Figure 24. eZ80F91 Module Schematic Diagram, #2 of 3—CPU and PHY UM014210-1003 PRELIMINARY Schematic Diagrams...

  • Page 78: Figure 25. Ez80F91 Module Schematic Diagram, #3 Of 3-Module

    74CBTLV3384 SO24.300 N.C. N.C. Flash 1Mx8 3.3V TSOP40.20MM MT28F008B3VG -CS0 -CSFLASH -DIS_FLASH -FLASH_EN -DIS_FLASH 74LCX32 TSSOP14 74LCX04 TSSOP14 -CS0 -CS0 -RESET -RESET -FLASHWE -FLASHWE 74LCX04 TSSOP14 Figure 25. eZ80F91 Module Schematic Diagram, #3 of 3—Module Memory UM014210-1003 PRELIMINARY Schematic Diagrams...

  • Page 79: General Array Logic Equations

    Development Kit User Manual Appendix A General Array Logic Equations This appendix shows the equations for disabling the Ethernet signals pro- vided by the U10 and U15 General Array Logic (GAL) devices. U10 Address Decoder //`defineidle2'b00 //`definestate12'b01 //`definestate22'b11 //`definestate32'b10...
  • Page 80 Development Kit User Manual nCS2, nEX_FL_DIS, //disables Flash on the expansion //module, when Low nEM_EN, //enables Development Platform LED //and Port A emulation circuit nDIS_FL, //disables Module Flash when Low nL_RD, //enables local data bus to be read by CPU...
  • Page 81 Development Kit User Manual output nCS_EX/* synthesis loc="P17"*/,//enables memory on the //Expansion Module nmemen1 /* synthesis loc="P18"*/,//enables memory on //the Development Platform nmemen2 /* synthesis loc="P19"*/, nmemen3 /* synthesis loc="P20"*/, nmemen4 /* synthesis loc="P21"*/, nEM_EN /* synthesis loc="P24"*/,//enables LED and...

  • Page 82: U15 Address Decoder

    Development Kit User Manual //wire nDIS_FL = (nFL_DIS) ? ~nEXP_EN : ~(nFL_DIS); wire nDIS_FL = nFL_DIS & nEXP_EN; //if either of them //is 0 Flash is //disabled assign nCS_EX = (nEX_FL_DIS) ? nEXP_EN : ~(nEX_FL_DIS); assign nL_RD = ~((nmemen1==0)|(nmemen2==0)|(nmemen3==0)|(nmemen4==0)|(nEM_EN==0)|( nCS_EX==0));...
  • Page 83 Development Kit User Manual module F92_em_pal( nDIS_EM, nEM_EN, nRD, nCS, nWR, nMREQ, nIORQ, nEM_RD, nEM_WR, nAN_WR, nCT_WR, nDIS_ETH input nDIS_EM /* synthesis loc="P3"*/, nEM_EN /* synthesis loc="P4"*/, /* synthesis loc="P5"*/, /* synthesis loc="P6"*/, /* synthesis loc="P10"*/, /* synthesis loc="P11"*/, /* synthesis loc="P12"*/,...
  • Page 84 Development Kit User Manual /* synthesis loc="P13"*/, /* synthesis loc="P27"*/, /* synthesis loc="P26"*/, nIORQ /* synthesis loc="P2"*/, /* synthesis loc="P7"*/, /* synthesis loc="P25"*/, //CS3 for CS9800 /* synthesis loc="P9"*/, nMREQ /* synthesis loc="P16"*/; output nEM_RD /* synthesis loc="P17"*/, nEM_WR /* synthesis loc="P18"*/,...
  • Page 85 Development Kit User Manual assign nCT_WR = ~((nDIS_EM==1)&(nWR==0)&(nEM_EN==0)&(address==cathode)); assign nDIS_ETH = ~(nCS); endmodule UM014210-1003 PRELIMINARY Appendix A...
  • Page 86 Development Kit User Manual General Array Logic Equations PRELIMINARY UM014210-1003...

  • Page 87: Customer Feedback Form

    Customer Feedback Form If you note any inaccuracies while reading this User Manual, please copy and complete this form, Return Information then mail or fax it to ZiLOG (see , below). We also welcome your sugges- tions! eZ80F91 Development Kit Serial # or Board Fab #/Rev.

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