ST STM32L4 5 Series Reference Manual page 1144

Basic timers (TIM6/TIM7)
33.4.4 TIM6/TIM7 status register (TIMx_SR)
Address offset: 0x10
Reset value: 0x0000
15 14 13
Res Res Res
Bits 15:1 Reserved, must be kept at reset value.
Bit 0 UIF: Update interrupt flag
This bit is set by hardware on an update event. It is cleared by software.
– At overflow or underflow regarding the repetition counter value and if UDIS = 0 in the
– When CNT is reinitialized by software using the UG bit in the TIMx_EGR register, if URS = 0
33.4.5 TIM6/TIM7 event generation register (TIMx_EGR)
Address offset: 0x14
Reset value: 0x0000
15 14 13
Res Res Res
Bits 15:1 Reserved, must be kept at reset value.
Bit 0 UG: Update generation
This bit can be set by software, it is automatically cleared by hardware.
0: No action.
1: Re-initializes the timer counter and generates an update of the registers. Note that the
prescaler counter is cleared too (but the prescaler ratio is not affected).
33.4.6 TIM6/TIM7 counter (TIMx_CNT)
Address offset: 0x24
Reset value: 0x0000
31 30 29
UIF
Res Res
CPY
r
15 14 13
rw rw rw
1144/1830
12 11 10 9
Res Res Res Res
0: No update occurred.
1: Update interrupt pending. This bit is set by hardware when the registers are updated:
TIMx_CR1 register.
and UDIS = 0 in the TIMx_CR1 register.
12 11 10 9
Res Res Res Res
28 27 26 25
Res Res Res Res
12 11 10 9
rw rw rw rw
8 7 6
Res Res Res
8 7 6
Res Res Res
24 23 22
Res Res Res
8 7 6
CNT[15:0]
rw rw rw
DocID024597 Rev 5
5 4 3 2
Res Res Res Res
5 4 3 2
Res Res Res Res
21 20 19 18
Res Res Res Res
5 4 3 2
rw rw rw rw
RM0351
1 0
Res UIF
rc_w0
1 0
Res UG
w
17 16
Res Res
1 0
rw rw