RM0351
Bit 31 UIFCPY: UIF Copy
This bit is a read-only copy of the UIF bit of the TIMx_ISR register. If the UIFREMAP bit in
TIMx_CR1 is reset, bit 31 is reserved and read as 0.
Bits 30:16 Reserved, must be kept at reset value.
Bits 15:0 CNT[15:0]: Counter value
33.4.7
TIM6/TIM7 prescaler (TIMx_PSC)
Address offset: 0x28
Reset value: 0x0000
15
14
13
rw
rw
rw
Bits 15:0 PSC[15:0]: Prescaler value
The counter clock frequency CK_CNT is equal to f
PSC contains the value to be loaded into the active prescaler register at each update event.
(including when the counter is cleared through UG bit of TIMx_EGR register or through
trigger controller when configured in "reset mode").
33.4.8
TIM6/TIM7 auto-reload register (TIMx_ARR)
Address offset: 0x2C
Reset value: 0xFFFF
15
14
13
rw
rw
rw
Bits 15:0 ARR[15:0]: Prescaler value
ARR is the value to be loaded into the actual auto-reload register.
Refer to
behavior.
The counter is blocked while the auto-reload value is null.
12
11
10
9
rw
rw
rw
rw
12
11
10
9
rw
rw
rw
rw
Section 33.3.1: Time-base unit on page 1135
DocID024597 Rev 5
8
7
6
5
PSC[15:0]
rw
rw
rw
rw
CK_PSC
8
7
6
5
ARR[15:0]
rw
rw
rw
rw
for more details about ARR update and
Basic timers (TIM6/TIM7)
4
3
2
rw
rw
rw
/ (PSC[15:0] + 1).
4
3
2
rw
rw
rw
1
0
rw
rw
1
0
rw
rw
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