ST STM32L4 5 Series Reference Manual page 1208

Real-time clock (RTC)
Bit 17 SUB1H: Subtract 1 hour (winter time change)
When this bit is set, 1 hour is subtracted to the calendar time if the current hour is not 0. This
bit is always read as 0.
Setting this bit has no effect when current hour is 0.
Bit 16 ADD1H: Add 1 hour (summer time change)
When this bit is set, 1 hour is added to the calendar time. This bit is always read as 0.
Bit 15 TSIE: Time-stamp interrupt enable
Bit 14 WUTIE: Wakeup timer interrupt enable
Bit 13 ALRBIE: Alarm B interrupt enable
Bit 12 ALRAIE: Alarm A interrupt enable
Bit 11 TSE: timestamp enable
Bit 10 WUTE: Wakeup timer enable
Bit 9 ALRBE: Alarm B enable
Bit 8 ALRAE: Alarm A enable
Bit 7 Reserved, must be kept at reset value.
Bit 6 FMT: Hour format
Bit 5 BYPSHAD: Bypass the shadow registers
Note: If the frequency of the APB clock is less than seven times the frequency of RTCCLK,
1208/1830
0: No effect
1: Subtracts 1 hour to the current time. This can be used for winter time change outside
initialization mode.
0: No effect
1: Adds 1 hour to the current time. This can be used for summer time change outside
initialization mode.
0: Time-stamp Interrupt disable
1: Time-stamp Interrupt enable
0: Wakeup timer interrupt disabled
1: Wakeup timer interrupt enabled
0: Alarm B Interrupt disable
1: Alarm B Interrupt enable
0: Alarm A interrupt disabled
1: Alarm A interrupt enabled
0: timestamp disable
1: timestamp enable
0: Wakeup timer disabled
1: Wakeup timer enabled
0: Alarm B disabled
1: Alarm B enabled
0: Alarm A disabled
1: Alarm A enabled
0: 24 hour/day format
1: AM/PM hour format
0: Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken from
the shadow registers, which are updated once every two RTCCLK cycles.
1: Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken
directly from the calendar counters.
BYPSHAD must be set to '1'.
DocID024597 Rev 5
RM0351