ST STM32L4 5 Series Reference Manual page 1216

Advanced arm-based 32-bit mcus
Table of Contents

Advertisement

Real-time clock (RTC)
38.6.8
RTC alarm B register (RTC_ALRMBR)
This register can be written only when ALRBWF is set to 1 in RTC_ISR, or in initialization
mode.
This register is write protected. The write access procedure is described in
write protection on page
Address offset: 0x20
Backup domain reset value: 0x0000 0000
System reset: not affected
31
30
29
MSK4
WDSEL
DT[1:0]
rw
rw
rw
15
14
13
MSK2
MNT[2:0]
rw
rw
rw
Bit 31 MSK4: Alarm B date mask
0: Alarm B set if the date and day match
1: Date and day don't care in Alarm B comparison
Bit 30 WDSEL: Week day selection
0: DU[3:0] represents the date units
1: DU[3:0] represents the week day. DT[1:0] is don't care.
Bits 29:28 DT[1:0]: Date tens in BCD format
Bits 27:24 DU[3:0]: Date units or day in BCD format
Bit 23 MSK3: Alarm B hours mask
0: Alarm B set if the hours match
1: Hours don't care in Alarm B comparison
Bit 22 PM: AM/PM notation
0: AM or 24-hour format
1: PM
Bits 21:20 HT[1:0]: Hour tens in BCD format
Bits 19:16 HU[3:0]: Hour units in BCD format
Bit 15 MSK2: Alarm B minutes mask
0: Alarm B set if the minutes match
1: Minutes don't care in Alarm B comparison
Bits 14:12 MNT[2:0]: Minute tens in BCD format
Bits 11:8 MNU[3:0]: Minute units in BCD format
Bit 7 MSK1: Alarm B seconds mask
0: Alarm B set if the seconds match
1: Seconds don't care in Alarm B comparison
Bits 6:4 ST[2:0]: Second tens in BCD format
Bits 3:0 SU[3:0]: Second units in BCD format
1216/1830
1193.
28
27
26
25
DU[3:0]
rw
rw
rw
rw
12
11
10
9
MNU[3:0]
rw
rw
rw
rw
DocID024597 Rev 5
24
23
22
21
MSK3
PM
HT[1:0]
rw
rw
rw
rw
8
7
6
5
MSK1
ST[2:0]
rw
rw
rw
rw
RM0351
RTC register
20
19
18
17
HU[3:0]
rw
rw
rw
rw
4
3
2
1
SU[3:0]
rw
rw
rw
rw
16
rw
0
rw

Advertisement

Table of Contents
loading
Need help?

Need help?

Do you have a question about the STM32L4 5 Series and is the answer not in the manual?

Table of Contents

Save PDF