Apb I/O Bus; O On Apb Bus; Boot Rom; Table 7: Access Type And Data Bit Width Of I/O - Siemens Ertec 400 Manual

3.2

APB I/O Bus

The APB bus is connected by means of an AHB/APB bridge on the multilayer AHB bus. The APB bus has a width
of 32 bits and operates at a frequency of 50 MHz.
4 I/O on APB bus
The ERTEC 400 block has multiple I/O function blocks. They are connected to the 32-bit APB I/O bus. The
ARM946E-S or PCI/LBU interface can access the I/O. The following I/O are available.
8 Kbyte Boot ROM
32-bit GPIO (*)
UART1, UART2
SPI interface
Timer 0, Timer 1
F-timer
Watchdog
System control register
(*) The complete 32 bits for GPIO input/output are only available if alternative functions are not assigned.
The I/O function blocks connected to the APB bus have data interfaces of different widths. The data bit width and
the supported access mechanisms are shown in the table below. Non-permitted access types such as byte-by-
byte loading of timer reload registers are not intercepted on the hardware side.
SUPPORTED ACCESS TYPES
Bit 31:24 Bit 23:16
8 bit
16 bit

Table 7: Access Type and Data Bit Width of I/O

Accesses to non-decoded-out memory or register areas trigger an FIQ interrupt. Access by a generated "Ready"
signal from the APB address decoder is closed. Write accesses do not affect the system. Read accesses supply
undefined data.
4.1

BOOT ROM

The ERTEC 400 is implemented with a BOOT ROM whose integrated opcode enables software to be
downloaded from an external storage medium. Various routines are available for the different boot and download
modes. In order to select the source and the mode, three BOOT[2:0] inputs are available on the ERTEC 400.
During the active reset phase, the boot pins are read in and stored in the BOOT REG register in the system
control register area.
After startup of the processor, the system branches to the appropriate BOOT routine based on the coding and the
download is performed. After the download is complete, the newly loaded functions are executed.
The following actions lead to a boot operation:
HW reset
•
Watchdog Reset
•
Software reset caused by setting the XRES_SOFT bit in the reset control register (system control
•
register area)
Copyright © Siemens AG 2010. All rights reserved.
Technical data subject to change
Bit 15:8
32 bit
8 bit 8 bit
32 bit
Bit 7:0 Function Block
Timer, F-counter,
Watchdog,
System control
register
Boot_Rom
8 bit
GPIO
16 bit
16 bit SPI
8 bit UART1/2
Page
33
ERTEC 400 Manual
Version 1.2.2