Page 1 Contents Introduction SIMATIC S5 User Program S5-155U Program Execution CPU 948 Operating Statuses and Program Execution Levels Programming Guide Interrupt and Error Diagnostics Integrated Special Functions This manual has the order number: 6ES5 998–3PR21 Extended Data Block DX 0 Memory Assignment and Memory...
Page 2 Trademarks SIMATIC , SIMATIC NET and SIMATIC HMI are registered trademarks of SIEMENS AG. Third parties using for their own purposes any other names in this document which refer to trademarks might infringe upon the rights of the trademark owners.
Page 3: Table Of Contents
Programming Tools ............1 - 18 Converting User Programs of the CPU 928B for the CPU 948......1 - 19 User Program .
Page 4 4.3.6 User Interfaces for Start-Up........... . . 4 - 24 4.3.7 Extended AUTOMATIC WARM RESTART with the CPU 948 (HOT RESTART)..4 - 27 4.3.8 Interruptions during START-UP .
Page 5 OB 202 to 205: Multiprocessor Communication ........6 - 62 CPU 948 Programming Guide...
Page 6 User Memory Organization in the CPU 948........
Page 7 10.8.4 Output Parameters ............10 - 51 CPU 948 Programming Guide...
Page 8 Indexes ..............13 - 3 CPU 948 Programming Guide...
Page 9: Introduction
Contents of Chapter 1 Area of Application for the S5-155U with the CPU 948 ......1 - 4 Typical Mode of Operation of a CPU .
Page 10 Contents CPU 948 Programming Guide 1 - 2 C79000-G8576-C848-04...
Page 11: Contents Of Chapter 1
This manual is intended to provide specialized information about programming the CPU 948 for users who already have basic knowledge of programming PLCs and want to use the CPU 948 in the S5-155U programmable controller. If you do not yet have this basic...
Page 12: Area Of Application For The S5-155U With The Cpu 948
Area of Application for the S5-155U with the CPU 948 SIMATIC S5 family The S5-155U programmable controller belongs to the family of SIMATIC S5 programmable controllers. With the CPU 948, it is the most powerful multiprocessor unit for process automation (open and closed loop control, signalling, monitoring, logging).
Page 13: Typical Mode Of Operation Of A Cpu
Output Q 2.0 Output process image image of the outputs are output by the of the outputs Output Q 3.1 system program to the output modules Output Q 4.7 assigned to the CPU. CPU 948 Programming Guide 1 - 5 C79000-G8576-C848-04...
Page 14: Typical Mode Of Operation Of A Cpu
Whether or not the time-controlled processing is more important than the interrupt controlled processing depends, among other things, on the particular task. For this reason, the priority of time and interrupt-driven processing on the CPU 948 can be selected. CPU 948 Programming Guide 1 - 6...
Page 15: The Programs In A Cpu
Update process image of the inputs Call System Output process image user of the outputs program processing (inter- Manage memory faces) Communication with Handle errors the PG Fig. 1-1 Tasks of the system program CPU 948 Programming Guide 1 - 7 C79000-G8576-C848-04...
Page 16 You can modify the system response by assigning parameters for the data block DX 0. Chapter 7 describes the system response following modification. When operating with several CPUs (multiprocessing) further tasks are involved. CPU 948 Programming Guide 1 - 8 C79000-G8576-C848-04...
Page 17 - at a time interval greater than the average cycle time, - at a specified point in time. Interrupt-driven processing Special, fast reactions to certain process signals. Error reaction Handling problems within the normal sequence of the program. CPU 948 Programming Guide 1 - 9 C79000-G8576-C848-04...
Page 18 Storing the user program After programming the user program, you must load it in the user memory of the CPU 948 (directly from the PG) or via a memory card whose contents are copied to the user memory by an OVERALL RESET of the CPU.
Page 19: Which Operands Are Available To The User Program
Which Operands are available to the User Program? Which Operands are available to the User Program? The CPU 948 provides the following operand areas for programming: • • process image and I/Os • • flags (F flags and S flags) •...
Page 20 IPC flags for data exchange between the CPUs. The bit test operations of the CPU 948 can also not be used with the S flags. These flags can only be used with the PG system software "S5-DOS"...
Page 21 In data blocks with a length greater than 256 words, you can only access data words with the numbers > 255 with operations for absolute memory access (refer to Chapter 9). CPU 948 Programming Guide 1 - 13 C79000-G8576-C848-04...
Page 22: How Much Memory Is Available For The User Program
How much Memory is available for the User Program? How much Memory is available for the User Program? For storing logic and data blocks, the CPU 948 only has the user memory in the internal RAM. The CPU 948 is available with two versions of the user memory: •...
Page 23: How To Tackle Programming
Create a list of the input and output signals required for the task. Improve the block diagram by assigning the signals and any particular time conditions and/or counter statuses to the individual blocks. CPU 948 Programming Guide 1 - 15 C79000-G8576-C848-04...
Page 24 It is often not constant, since the cyclic user program may be interrupted when time and interrupt-driven program sections are called. CPU 948 Programming Guide 1 - 16 C79000-G8576-C848-04...
Page 25 The more complex the process, the greater the risk and therefore the greater the care required when starting up. CPU 948 Programming Guide 1 - 17 C79000-G8576-C848-04...
Page 26: Programming Tools
ST 59 /9/. Note If you wish to use the full range of performance of the CPU 948 in your automation software, (particularly the DX 0 screen, the "Output ISTACK" screen, the display with the "memory configuration"...
Page 27: Converting User Programs Of The Cpu 928B For The Cpu 948
Converting User Programs of the CPU 928B for the CPU 948 Converting User Programs of the CPU 928B for the CPU 948 The following section informs you about the points you should remember when you convert user programs written for the CPU 928B for use on the CPU 948.
Page 28 Converting User Programs of the CPU 928B for the CPU 948 Timer processing CPU 928B CPU 948 The timers are updated during The timers are only updated in start-up. the RUN mode (Reason: compatibility with CPU 946/947) FB 0 as cycle block...
Page 29 With the CPU 928B, the RT area is not used by the system program, with the CPU 948 it is used to some extent by the handling blocks. You can only use the RT area for your user program when you do not use any standard FBs and any PG functions via SINEC H1 and the S5 bus.
Page 30 Standard FBs Generally, the standard function blocks used on the CPU 928B (e.g. for IPs) must be replaced by those for the CPU 948. The HDBs are an exception these can be taken from the CPU 928B (see Section 1.8.1).
Page 31: User Program
Special Data Blocks ........... . 2 - 41 CPU 948 Programming Guide...
Page 32 Contents CPU 948 Programming Guide 2 - 2 C79000-G8576-C848-04...
Page 33 User Program The following chapter explains the components that make up a STEP 5 user program for the CPU 948 and how it can be structured. CPU 948 Programming Guide 2 - 3 C79000-G8576-C848-04...
Page 34: Step 5 Programming Language
While the ladder diagram (LAD) and control system flowchart (CSF) list of statements methods of representation represent your STEP 5 program graphically, statement list (STL) represents STEP 5 operations individually as mnemonic abbreviations. CPU 948 Programming Guide 2 - 4 C79000-G8576-C848-04...
Page 35: Structured Programming
Using STEP 5, you can structure your program by dividing it into self-contained program sections (blocks). This division of your program clarifies the essential program structures making it easy to recognize the system parts that are related within the software. CPU 948 Programming Guide 2 - 5 C79000-G8576-C848-04...
Page 36: Step 5 Operations
Example Parameter Operation code F 54.1 Operand Operation (what is to be done?) (with what is the operation to be done?) CPU 948 Programming Guide 2 - 6 C79000-G8576-C848-04...
Page 37 Section 3.5 describes the whole STEP 5 operation set and explains how the RLO is obtained. This section also includes programming examples for individual STEP 5 operations. CPU 948 Programming Guide 2 - 7 C79000-G8576-C848-04...
Page 38: Number Representation
+D and -D they can also be used for addition and subtraction. The STEP 5 programming language also has conversion operations that enable you to convert numbers directly to the most important of the other numerical representations. CPU 948 Programming Guide 2 - 8 C79000-G8576-C848-04...
Page 39 The mantissa is 24 bits long and the exponent is 8 bits long. In the CPU 948, the default mantissa is 24 bits long (bits 0 to 23) for adding, subtracting, multiplying and dividing. The exponent indicates the order of magnitude of the floating point number.
Page 40 ± 0.1469368 x 10 to ± 0.1701412 x 10 Permissible numerical range Input/output on PG in a logic block: You want to load the number N = 12.34567 as a floating point number. Input: :LKG1234567+2 CPU 948 Programming Guide 2 - 10 C79000-G8576-C848-04...
Page 41 1001 (0 and 9 decimal). The left bits are reserved for the sign as follows: Sign for a positive number: 0000 Sign for a negative number: 1111 Permissible numerical range -999 to +999 CPU 948 Programming Guide 2 - 11 C79000-G8576-C848-04...
Page 42: Step 5 Blocks And Storing Them In Memory
GRAPH 5/4/. Sequence blocks have therefore lost their original significance in STEP 5. Sequence blocks now represent an extension of the program blocks and are used as program blocks. CPU 948 Programming Guide 2 - 12 C79000-G8576-C848-04...
Page 43 Depending on the block type, the block body contains the following: • • STEP-5 operations (in OB, PB, SB, FB, FX), • • variable or constant data (in DB, DX) • • a formal operand list (in FB, FX). CPU 948 Programming Guide 2 - 13 C79000-G8576-C848-04...
Page 44 These are reserved for specific functions and you cannot use them as normal data blocks. Data block DX 2 is reserved for the 2nd serial interface and you should not use it. CPU 948 Programming Guide 2 - 14 C79000-G8576-C848-04...
Page 45 You can use the COMPRESS MEMORY online function to make space for new blocks. This function optimizes the utilization of the memory by deleting blocks marked as invalid and shifting valid blocks together. CPU 948 Programming Guide 2 - 15 C79000-G8576-C848-04...
Page 46: Program, Organization And Sequence Blocks
You can program block calls inside an organization, program, function or sequence block. They can be compared with jumps to a subroutine. Each jump causes a block change. The return address within the calling block is buffered by the system. CPU 948 Programming Guide 2 - 16 C79000-G8576-C848-04...
Page 47 PB 1 PB 5 PB 10 PB 10 PB 5 F 1.5 I 5.3 PB 6 I 1.5 PB 6 I 3.2 Fig. 2-3 Block calls that enable processing of a program block CPU 948 Programming Guide 2 - 17 C79000-G8576-C848-04...
Page 48: Organization Blocks As User Interfaces
(JC/JU OB xxx). It is, however, not possible to trigger a COLD RESTART, e.g. by calling OB 20. The following table provides you with an overview of the user interfaces (OBs). CPU 948 Programming Guide 2 - 18 C79000-G8576-C848-04...
Page 49 Program, Organization and Sequence Blocks Table 2-1 Overview of the organization blocks of the CPU 948 for program execution Organization blocks for controlling program execution Block Function and call criterion OB 1 Organization of cyclic program execution; first call after a start-up, then cyclic call.
Page 50 Organization of the cyclic program for communication in the "soft stop" mode. Table 2-4 Overview of the organization blocks of the CPU 948 for error handling Organization blocks for reaction to device or program errors Block Function and call criterion...
Page 51 (logic block not loaded), OB 23 or OB 24, OB 29 (timeout) or OB 33 (collision of timed interrupts) do not exist, there is no reaction! OB 31 only exists in the CPU 948 for the sake of compatibility. To set the cycle monitoring time, you should use data block DX0 (refer to Chapter 7) OB 31 is called once during the start-up, if loaded.
Page 52: Organization Blocks For Special Functions
They do not contain a STEP 5 program. Special function OBs can be called in all logic blocks. Table 2-5 Overview of the organization blocks of the CPU 948 for special functions Integrated organization blocks with special functions Block: Block function:...
Page 53: Function Blocks
In the user program, each function block represents a complex complete function. You can obtain function blocks as follows: • • as a software product from SIEMENS (standard function blocks on diskette - see /11/); with these function blocks you can generate user programs for fast and simple open loop control, signalling, closed loop control and logging;...
Page 54: Structure Of Function Blocks
3 words formal operands Formal operand 2 3 words Block body Formal operand 3 words 1st STEP 5 user operation STEP 5 user program Fig. 2-4 Structure of a function block (FB/FX) CPU 948 Programming Guide 2 - 24 C79000-G8576-C848-04...
Page 55 First program the FB/FX with the formal operands and keep it on the PG (offline) or in the CPU memory (online) Then program the block(s) to be called with the actual operands. CPU 948 Programming Guide 2 - 25 C79000-G8576-C848-04...
Page 56: Programming Function Blocks
(STL). The formal operands are preceded by an equality sign (e.g. A = X1). They can also be referenced more than once at various positions in the function block. Terminate your program input with the block end operation "BE". CPU 948 Programming Guide 2 - 26 C79000-G8576-C848-04...
Page 57 The data type indicates whether you are working with bits, bytes, words or double words for I and Q parameters and which data format applies to D parameters (e.g. bit pattern or hexadecimal pattern). CPU 948 Programming Guide 2 - 27 C79000-G8576-C848-04...
Page 58: Calling Function Blocks And Assigning Parameters To Them
After the unconditional or conditional call, the RLO can no longer be combined logically. However, it is carried over to the called function block with the jump and can be evaluated there. CPU 948 Programming Guide 2 - 28 C79000-G8576-C848-04...
Page 59 (BCD- coded) units .0 to .3 and values 0 to 999 for a counter value 0 to 999 CPU 948 Programming Guide 2 - 29 C79000-G8576-C848-04...
Page 60 When the program returns from the called function block, the list of actual operands in the calling block is skipped by a jump operation activated implicitly by STEP 5 in MC-5 code. CPU 948 Programming Guide 2 - 30 C79000-G8576-C848-04...
Page 61 INP1 OUT1 Q 23.0 INP2 : F 17.7 F 17.7 INP2 OUT1 : Q 23.0 : BE Formal Actual operands operands The following operations are executed after the jump to FB 202 CPU 948 Programming Guide 2 - 31 C79000-G8576-C848-04...
Page 62 LOOP : : BE Formal Actual operands operands CSF/LAD method of representation PB 25 SEGMENT 1 FB 201 REQUEST DW 1 DATA TRAN I 3.5 F 2.5 LOOP MTIM KT 010.1 TIME CPU 948 Programming Guide 2 - 32 C79000-G8576-C848-04...
Page 63: Special Function Blocks
32-bit floating point number, is written to DD 10. Prior to this, the appropriate data block must be opened. The parameter VZ (parameter type: Q, data type: BI) indicates the sign of the radicand: VZ = 1 for a negative radicand. CPU 948 Programming Guide 2 - 33 C79000-G8576-C848-04...
Page 64 SQRT DD 10 SQRT : DD 10 DD= data double word *) Must be located in separate segments, since the operation "C DB 17" in segment 1 cannot be converted to LAD/CSF. CPU 948 Programming Guide 2 - 34 C79000-G8576-C848-04...
Page 65: Data Blocks
PLC and then transfer it back to diskette, otherwise all the data words in the DB are automatically assigned the data format you selected in the presets screen form. CPU 948 Programming Guide 2 - 35 C79000-G8576-C848-04...
Page 66 A data block can occupy a total of maximum 32 767 words (including header) in the CPU memory. When you use your programmer to enter and transfer data blocks, remember the size of your CPU memory! CPU 948 Programming Guide 2 - 36 C79000-G8576-C848-04...
Page 67: Creating Data Blocks
Data formats permitted in a data block Type Data format Examples Bit pattern 00100110 00111111 Hexadecimal 263F 2 Bytes 038,063 Fixed point number +09791 Floating point number +1356123+12 Character ?!ABCD123-+.,% Timer value 055.2 Counter value CPU 948 Programming Guide 2 - 37 C79000-G8576-C848-04...
Page 68: Opening Data Blocks
ACCU 1. The contents of a data word are not changed. A transfer operation transfers data from ACCU 1 to the referenced data word. The old contents of the data word are overwritten. CPU 948 Programming Guide 2 - 38 C79000-G8576-C848-04...
Page 69 DB 10 (open DB 10) DW 1 (load the contents of DW 1 into ACCU 1) DB 20 (open DB 20) DW 1 (transfer the contents of ACCU 1 to DW 1) CPU 948 Programming Guide 2 - 39 C79000-G8576-C848-04...
Page 70 PB 20 C DB 10 JU PB 20 C DB 11 Range of validity of DB 10 Range of validity of DB 11 Fig. 2-5 Range of validity of an opened data block CPU 948 Programming Guide 2 - 40 C79000-G8576-C848-04...
Page 71: Special Data Blocks
2.4.3 Special Data Blocks On the CPU 948 data blocks DB 0, DB 1, DX 0, DX 1 and DX 2 are reserved for special functions. They are managed by the system program and you cannot use them freely for other functions.
Page 72 Data Blocks CPU 948 Programming Guide 2 - 42 C79000-G8576-C848-04...
Page 73: Program Execution
Semaphore Operations ........... 3 - 75 CPU 948 Programming Guide...
Page 74 Contents CPU 948 Programming Guide 3 - 2 C79000-G8576-C848-04...
Page 75: Program Execution
The chapter therefore deals with the basics of STEP 5 programming and explains in detail (with examples) the STEP 5 operations for the CPU 948. Experienced readers who require more information about a specific STEP 5 operation listed in the Pocket Guide can refer to the reference section in 3.5.
Page 76: Principle Of Program Execution
Up d a t e in t e r - p r o c e s s o r c o m m . f la g o u t p u t s Fig. 3-1 Principle of cyclic program execution CPU 948 Programming Guide 3 - 4 C79000-G8576-C848-04...
Page 77: Program Organization
Figs. 3-2 and 3-3 are examples of a program structure. CPU 948 Programming Guide 3 - 5 C79000-G8576-C848-04...
Page 78 Fig. 3-2 Example of the organization of the user program according to the program structure CPU 948 Programming Guide 3 - 6 C79000-G8576-C848-04...
Page 79 D a t a l o g g i n g o u t p u t Fig. 3-3 Example of the organization of the user program according to the structure of the controlled system CPU 948 Programming Guide 3 - 7 C79000-G8576-C848-04...
Page 80 STEP 5 statement after the block call. The CPU also stores the start address and length of the data block valid at this location. CPU 948 Programming Guide 3 - 8 C79000-G8576-C848-04...
Page 81 (in the example: 2 + 2 + 1 + 0 = 5). - Add the two amounts together to obtain the program nesting depth (in the example: 4 + 5 = nesting depth 9). It must not exceed a value of 40. CPU 948 Programming Guide 3 - 9 C79000-G8576-C848-04...
Page 82: Storing Program And Data Blocks
Storing Program and Data Blocks Storing Program and Data Blocks On the CPU 948, the user program runs solely in the internal RAM. The user program including data blocks must, therefore, be loaded in the CPU 948 user memory. How do I load programs and...
Page 83: Processing The User Program
After the system functions have been executed at the beginning of a CYCLE, the system program calls organization block OB 1 or function block FB 0 as the cyclic user program. You program the STEP 5 operations for cyclic processing in this block. CPU 948 Programming Guide 3 - 11 C79000-G8576-C848-04...
Page 84: Definition Of Terms Used In Program Execution
(OB 2 to OB 18 for interrupt servicing, OB 19 and OB 23 to OB 34 for reactions to errors) are available on the CPU 948. You can store an appropriate STEP 5 program in these blocks. When interrupts or errors are to be processed, the system program activates the corresponding organization block during cyclic processing.
Page 85 IPC flags to the coordinator or to the communications processors. You define the input and output IPC flags when you create data block DB 1 (refer to Section 10.1.6). CPU 948 Programming Guide 3 - 13 C79000-G8576-C848-04...
Page 86 • • a device hardware fault or program error • • operator intervention (using the PC stop function, or setting the mode selector to "stop", multiprocessor stop MP-STP), • • a stop operation CPU 948 Programming Guide 3 - 14 C79000-G8576-C848-04...
Page 87: Step 5 Operations With Examples
• • semaphore operations (can only be used in FB/FX function blocks). Accumulators as working The CPU 948 has four accumulators, ACCU 1 to ACCU 4. Most registers STEP 5 operations use two 32-bit registers (ACCU 1 and ACCU 2) as the source of operands and the destination for results.
Page 88 ERAB to 0; the RLO can be evaluated (e.g. by RLO-dependent operations) but can no longer be combined logically. The next binary logic operation following a binary set/reset operation is once again a first bit scan. CPU 948 Programming Guide 3 - 16 C79000-G8576-C848-04...
Page 89 • • OS Stored overflow The overflow bit is stored. It can be used in several arithmetic operations to indicate whether an overflow occurred at any point during the operations. CPU 948 Programming Guide 3 - 17 C79000-G8576-C848-04...
Page 90 When a change of level takes place, e.g. servicing a timed interrupt, all accumulators and the bit and word condition codes (RLO etc.) are saved and loaded again when the interrupted level is resumed. CPU 948 Programming Guide 3 - 18 C79000-G8576-C848-04...
Page 91: Basic Operations
At the beginning of a logic sequence, the RLO only depends on the signal state scanned (first scan) and not on the type of logic operation (O = OR, A = AND). CPU 948 Programming Guide 3 - 19 C79000-G8576-C848-04...
Page 92 Q 0.0 to 127.7 an output in the PIQ F 0.0 to 255.7 a flag S 0.0 to 4095.7 an S flag D 0.0 to 255.15 a bit in the data word CPU 948 Programming Guide 3 - 20 C79000-G8576-C848-04...
Page 93 (P area) 0 to 255 a byte of the extended I/O area (O area) 0 to 254 a word of the extended I/O area (O area) CPU 948 Programming Guide 3 - 21 C79000-G8576-C848-04...
Page 94 Load operations write the addressed value into ACCU 1. The former contents of ACCU 1 are saved in ACCU 2 (stack lift). Transfer operations Transfer operations write the contents of ACCU 1 to the addressed memory location. CPU 948 Programming Guide 3 - 22 C79000-G8576-C848-04...
Page 95 ACCU 1 L FD k k + 1 T FD k k + 2 k + 3 only with load operations Fig. 3-6 Load and transfer operations in a byte-oriented memory area CPU 948 Programming Guide 3 - 23 C79000-G8576-C848-04...
Page 96 Load and transfer operations in a word-oriented memory area Note Load operations do not affect the condition codes. Transfer operations clear the OS bit. When a byte or word is loaded the extra bits are cleared in ACCU 1. CPU 948 Programming Guide 3 - 24 C79000-G8576-C848-04...
Page 97 If you use relative addresses of the O peripherals in an expansion unit, you can no longer use these addresses for I/O modules in the central controller (this would result in double addressing). CPU 948 Programming Guide 3 - 25 C79000-G8576-C848-04...
Page 98 When executing the timer or counter operations SP T, SE T, SD T, SS T, SF T and S C the value in ACCU 1 is transferred to the timer or counter (as with the transfer operation) and the appropriate operation is started. CPU 948 Programming Guide 3 - 26 C79000-G8576-C848-04...
Page 99 When using timers, you should therefore select the smallest possible time base (time base < timer value): Example: time value 4s not: 1 s x 4 inaccuracy: 1 s but: 0.01 s x 400 inaccuracy: 0.01 s CPU 948 Programming Guide 3 - 27 C79000-G8576-C848-04...
Page 100 In the timer or counter itself, the value is in binary code. If you want to scan the timer or counter, you can load the actual timer or counter value into ACCU 1 directly or in BCD code. CPU 948 Programming Guide 3 - 28 C79000-G8576-C848-04...
Page 101 The time base is not loaded. Loading counter values directly: Counter value Counter C 10 ACCU 1 ’0’ "L C 10": Loads the binary counter value of counter C 10 directly into ACCU 1 CPU 948 Programming Guide 3 - 29 C79000-G8576-C848-04...
Page 102 If you load values in BCD, status bits 14 and 15 of the timer or 12 to 15 of the counter are not loaded. They have the value 0 in ACCU 1. The value in the ACCU can now be processed further. CPU 948 Programming Guide 3 - 30 C79000-G8576-C848-04...
Page 103 <ACCU 1> <ACCU 2> <ACCU 3> <ACCU 4> after: <result> <ACCU 3> <ACCU 4> <ACCU 4> Note Within the supplementary operations, there are operations for subtraction and addition of double word fixed point numbers. CPU 948 Programming Guide 3 - 31 C79000-G8576-C848-04...
Page 104 3 to 255 Generate data block DX (ACCU 1 must contain the number of data words – maximum 4091 – that the new block is to have ) only for test purposes! CPU 948 Programming Guide 3 - 32 C79000-G8576-C848-04...
Page 105 To make diagnosis easier, you should set an identifier before calling the STP operation, e.g. a special bit pattern in a diagnostic DB or use the STEP 5 operation STS (refer to Section 3.5.4). CPU 948 Programming Guide 3 - 33 C79000-G8576-C848-04...
Page 106: Programming Examples In The Stl, Lad And Csf Methods Of Representation
Output Q 3.5 is "1" when all inputs are "1" simultaneously Output Q 3.5 is "0" if any of the inputs has signal state "0" The number of scans and the sequence of the logic statements are optional CPU 948 Programming Guide 3 - 34 C79000-G8576-C848-04...
Page 107 Q 3.1 I 1.4 Q 3.1 I 1.3 Q3.1 Q 3.1 Q 3.1 is "1" when at least one AND condition is satisfied Q 3.1 is "0" when no AND condition is satisfied CPU 948 Programming Guide 3 - 35 C79000-G8576-C848-04...
Page 108 & Q3.0 I 2.1 Q 3.0 Q3.0 Output Q 3.0 is "1" when both OR conditions are satisifed Output Q 3.0 is "0" when at least one OR condition is not satisfied CPU 948 Programming Guide 3 - 36 C79000-G8576-C848-04...
Page 109 When the set signal (input I 2.7) and the reset signal (input I 1.4) are applied at the same time, the scan operation programmed last (in this case AI 1.4) remains in effect for the rest of the program (reset priority). CPU 948 Programming Guide 3 - 37 C79000-G8576-C848-04...
Page 110 When the set signal (input I 2.6) and the reset signal (input I 1.3) are applied at the same time, the scan operation last programmed (in this case AI 1.3) remains in effect for the rest of the program (reset priority). CPU 948 Programming Guide 3 - 38 C79000-G8576-C848-04...
Page 111 The binary scaler (output Q 3.2) changes its state each time input I 1.0 changes its signal state from 0 to 1 (leading edge). Therefore, only half the input frequency appears at the output of the memory cell. CPU 948 Programming Guide 3 - 39 C79000-G8576-C848-04...
Page 112 3 = 10 sec BI and DE are digital outputs of the timer. The time at output BI is in binary code. The time at DE is in BCD code with time base. CPU 948 Programming Guide 3 - 40 C79000-G8576-C848-04...
Page 113 IW 15: Set the timer with the value of the operand I, Q, F or I 3.1 D in BCD code (in this example, input word 15). Q4.1 CPU 948 Programming Guide 3 - 41 C79000-G8576-C848-04...
Page 114 The timer is loaded with the specified value (9). The I 3.5 Q4.2 number to the right of the decimal point indicates the time base: 0 = 0.1sec 2 = 10 sec 1 = 0.1 sec 3 = 10 sec CPU 948 Programming Guide 3 - 42 C79000-G8576-C848-04...
Page 115 When the RLO is "1", the timer is reset (cleared). The scan AT or OT produces signal state "1" if the timer is running or the RLO at the input is "1". CPU 948 Programming Guide 3 - 43 C79000-G8576-C848-04...
Page 116 Q 2.4 Q 2.4 =0 / 16 bits I 4.2 Q 2.4 An RLO of "1" (I 4.2) resets the counter to zero. An RLO of "0" does not affect the counter. CPU 948 Programming Guide 3 - 44 C79000-G8576-C848-04...
Page 117 Owing to the two separate edge flags for CU and CD, a counter with two different inputs can be used as an up/down counter. CPU 948 Programming Guide 3 - 45 C79000-G8576-C848-04...
Page 118 Owing to the two separate edge flags for CU and CD, a counter with two different inputs can be used as an up/down counter. CPU 948 Programming Guide 3 - 46 C79000-G8576-C848-04...
Page 119 ACCU 2 (32 bits) are compared with each other. During the comparison, the numerical representation of the operands is taken into account, i.e. the contents of ACCU-1-L and ACCU-2-L are interpreted here as a fixed point number. CPU 948 Programming Guide 3 - 47 C79000-G8576-C848-04...
Page 120 "less than or equal to" (see the operations list). During the comparison, the numerical representation of the operands is taken into account, i.e. the contents of ACCU-1-L and ACCU-2-L are interpreted here as a fixed point number. CPU 948 Programming Guide 3 - 48 C79000-G8576-C848-04...
Page 121: Supplementary Operations
(LAD and CSF methods of representation). This section describes the supplementary operations and covers possible combinations of substitution operations with actual operands. System operations System operations are marked in the first column of the tables with CPU 948 Programming Guide 3 - 49 C79000-G8576-C848-04...
Page 122 Exklusive OR operation on the contents of ACCU-1-L and ACCU-2-L ACCUs 2, 3 and 4 are not affected, however, the condition codes CC 1 and CC 0 are affected (see word condition codes). CPU 948 Programming Guide 3 - 50 C79000-G8576-C848-04...
Page 123 RS area RT 0.0 to 255.15 of a bit in RT area The bit test operations scan the state of the bit and indicate it via the RLO. CPU 948 Programming Guide 3 - 51 C79000-G8576-C848-04...
Page 124 RI area 0.0 to 255.15 of a bit in RJ area 60.0 to 63.15 of a bit in RS area 0.0 to 255.15 of a bit in RT area CPU 948 Programming Guide 3 - 52 C79000-G8576-C848-04...
Page 125 RLO (change from 0 to 1). The counter is only started if the RLO = 1 at the time of the start operation. for SP T for FR T Scan with A T CPU 948 Programming Guide 3 - 53 C79000-G8576-C848-04...
Page 126 BILL : I 10.4 =BILL I 10.4 JACK : T 18 =EGON IW 20 EGON : IW 20 :SEC =JACK T 18 YOGI : F 100.7 =JACK T 18 =YOGI F 100.7 CPU 948 Programming Guide 3 - 54 C79000-G8576-C848-04...
Page 127 (KH), two absolute numbers of 1 byte each (KY), a character (KS), a fixed point number (KF), a timer value (KT) and a counter value (KC). For "LWD=" permissible data is a floating point number. CPU 948 Programming Guide 3 - 55 C79000-G8576-C848-04...
Page 128 RS 63 of the RS area. Refer to Section 8.3.4 "RS/RT Area". You can use the RT area in its complete length (RT 0 to RT 255) providing you do not use any standard function blocks. CPU 948 Programming Guide 3 - 56 C79000-G8576-C848-04...
Page 129 The following fraction must be calculated: (30 + 3 * 4) / 6 = 7 ACCU 1 ACCU 2 ACCU 3 ACCU 4 Contents of the ACCUs before the sequence of arithmetic operations L KF +30 L KF +3 L KF +4 L KF +6 CPU 948 Programming Guide 3 - 57 C79000-G8576-C848-04...
Page 130 Swap the contents of ACCU 1 and ACCU 2 Programming is dependent on the PG type and the release of the PG system software. For changes in ACCU 2 and ACCU 3: see Section 3.5.1 "Basic Operations/Arithmetic Operations". CPU 948 Programming Guide 3 - 58 C79000-G8576-C848-04...
Page 131: Executive Operations
If the RLO is 0, the statement is not executed and the RLO is set to 1. Jump if result is ’0’ : the jump is executed only if CC 1 is 0 and CC 0 is 0. The RLO is not changed. CPU 948 Programming Guide 3 - 59 C79000-G8576-C848-04...
Page 132 (negative operand) address than the current operation. Caution If you use JUR incorrectly, undefined statuses can occur in the system. It should only be used by extremely experienced programmers with detailed knowledge of the system. CPU 948 Programming Guide 3 - 60 C79000-G8576-C848-04...
Page 133 Shift operations are executed regardless of conditions. You can use jump operations to scan the value of the last bits shifted out using CC 1/CC 0. Shift: last CC 1 CC 0 Jump operation bit shifted CPU 948 Programming Guide 3 - 61 C79000-G8576-C848-04...
Page 134 Caution: FW 10 do not exceed the positive area limit! 4. Application: Division by the 2nd power, e.g. new value = old value : 4 DB 5 DW 0 :SRW DW 0 CPU 948 Programming Guide 3 - 62 C79000-G8576-C848-04...
Page 135 15 14 ....2 ↓ ↑ S S S S S (sign): 0 = positive 1 = negative CPU 948 Programming Guide 3 - 63 C79000-G8576-C848-04...
Page 136 (base 2). After the multiplication, remnants of the original mantissa remain to the right of the imaginary decimal point. These bit places are cut off from the whole result. CPU 948 Programming Guide 3 - 64 C79000-G8576-C848-04...
Page 137 51 with a reversed sign. STEP 5 program: Assignment of the data words: :L DW 207 KF = +51 :CSW :T DW 51 KF = -51 CPU 948 Programming Guide 3 - 65 C79000-G8576-C848-04...
Page 138 F flag and executed. DO = Process formal operand (parameter type B): Only C DB, JU PB, JU OB, JU FB, JU SB can be substituted. Insert formal operand CPU 948 Programming Guide 3 - 66 C79000-G8576-C848-04...
Page 139 JU=, JC=, JZ=, JN=, JP=, JM=, JO=, SLW, SRW, D, I, SED, SEE, C DB, JU.. , JC.., G DB, GX DX, CX DX, DOC FX, DOU FX. The PG does not check the legality of the combinations! CPU 948 Programming Guide 3 - 67 C79000-G8576-C848-04...
Page 140 DW 0 DW 1 increment the index register KF +1 DW 1 KF +100 :<=F =M001 jump if the index is within the range remaining STEP 5 program Continued on next page CPU 948 Programming Guide 3 - 68 C79000-G8576-C848-04...
Page 141 (parameter word) depends on the operation you are using. Parameter word for inputs and outputs Bit no. 11 10 no significance Bit address Byte address from 0 to 127 from 0 to 7 CPU 948 Programming Guide 3 - 69 C79000-G8576-C848-04...
Page 142 Parameter word for timers and counters Bit no. no significance Number of timer or counter cell from 0 to 255 Principle of the substitution with a binary operation 11 10 DW 27 DO DW statement executed CPU 948 Programming Guide 3 - 70 C79000-G8576-C848-04...
Page 143 Principle of sequence in FB 1 FW 10 4A5AH FW 16 0001H FW 12 xxxxH yyyyH FW 14 FW 16 ACCU 1 0001H (cons. no. of actual operand) :L IB 90 Operation executed with "DI" CPU 948 Programming Guide 3 - 71 C79000-G8576-C848-04...
Page 144 Set interrupt mask (UAMW) (32 bits): before calling the operation, the bit pattern for the mask must be loaded in ACCU 1 (32 bits) Read interrupt mask: bit pattern of the interrupt mask (32 bits) is loaded in ACCU 1 CPU 948 Programming Guide 3 - 72 C79000-G8576-C848-04...
Page 145 HALT Stop instruction from coordinator COR Single step mode Address comparison active INTAS Interrupt from SPU processor Clock failure of SPU processor DARY Continuous ready (access to faulty memory) Bracket counter overflow CPU 948 Programming Guide 3 - 73 C79000-G8576-C848-04...
Page 146 STUEU ISTACK overflow Power failure Timed interrupt (delayed interrupt, clock-controlled interrupt Timeout Addressing error PARE Parity error Cycle time error STOP Mode selector switched to STOP HOLD DMA request from SPU processor CPU 948 Programming Guide 3 - 74 C79000-G8576-C848-04...
Page 147: Semaphore Operations
Standard FBs, handling blocks and blocks for multiprocessor communication manage the coordination internally. If you use these blocks, you do not need to program the operations SEE xx and SED xx. CPU 948 Programming Guide 3 - 75 C79000-G8576-C848-04...
Page 148 E n a b l e se m a p h o r e : E n d Fig. 3-8 Coordination of access to the global memory CPU 948 Programming Guide 3 - 76 C79000-G8576-C848-04...
Page 149 COLD RESTART, all the semaphores are cleared. During a manual or automatic warm restart, the semaphores are retained. • • Start-up in multiprocessor operation must be synchronized. For this reason, no test operation is allowed. CPU 948 Programming Guide 3 - 77 C79000-G8576-C848-04...
Page 150 F 10.2 = 1: the timer was started F 10.3 = 1: the message was transmitted F 10.4 = 1: the semaphore was re-enabled Continued on next page CPU 948 Programming Guide 3 - 78 C79000-G8576-C848-04...
Page 151 T 10 and the timer has elapsed, FB 101 call "enable semaphore" FB. NAME :SEMAENAB 10.4 If the semaphore is enabled, :BEC KH0000 FY10 reset all flags. Continued on next page CPU 948 Programming Guide 3 - 79 C79000-G8576-C848-04...
Page 152 F 10.3 F 10.3 Set "TRANSFER MESSAGE" flag FB 101 NAME :SEMAENAB :SEE 10 Enable semaphore no. 10 =M001 F 10.4 F 10.4 Set "SEMAPHORE ENABLED" flag M001 :BE CPU 948 Programming Guide 3 - 80 C79000-G8576-C848-04...
Page 153: Operating Statuses And Program Execution Levels
User Interfaces for Start-Up ..........4 - 24 4.3.7 Extended AUTOMATIC WARM RESTART with the CPU 948 (HOT RESTART) . . . 4 - 27 4.3.8 Interruptions during START-UP .
Page 154 Contents CPU 948 Programming Guide 4 - 2 C79000-G8576-C848-04...
Page 155: Operating Statuses And Program Execution Levels
Execution Levels This chapter provides an overview of the operating statuses and program execution levels of the CPU 948. It informs you in detail about various types of start-up and the organization blocks associated with them, in which you can program your own sequences for various situations when restarting.
Page 156: Program Execution Levels
TRAF START-UP COLD RESTART WARM RESTART PARE START-UP FEDBX Time-controlled program execution TIMED INTERRUPTS WEFES/WEFEH Interrupt-driven TRAF program execution PROCESS INTERRUPTS/INTERRUPTS PARE FEDBX Cyclic program execution CYCLE Fig. 4-1 Program execution levels CPU 948 Programming Guide 4 - 4 C79000-G8576-C848-04...
Page 157 Interrupt stack (ISTACK) If an interrupt occurs, the system program sets up an information field in the ISTACK for each level, to allow it to continue in the interrupted level after servicing the interrupt. CPU 948 Programming Guide 4 - 5 C79000-G8576-C848-04...
Page 158 OB, the CPU continues the program execution at the point of interruption (including all the blocks nested there) as long as no stop is programmed in the OB. CPU 948 Programming Guide 4 - 6 C79000-G8576-C848-04...
Page 159 "Execution by the system program": At the CYCLE program execution level, the system program updates the process image of the inputs and outputs, triggers the cycle monitoring time and calls the PG interface management (system checkpoint). CPU 948 Programming Guide 4 - 7 C79000-G8576-C848-04...
Page 160 TIMED INTERRUPT level nested in. If an addressing error now occurs while servicing the timed interrrupt, the timed interrupt servicing is interrupted immediately at the next operation boundary to nest in the ADF level. CPU 948 Programming Guide 4 - 8 C79000-G8576-C848-04...
Page 161: Stop Mode
STOP Mode STOP Mode The CPU 948 has two different STOP modes, the "hard" STOP and the "soft" STOP (= CPU capable of communication). 4.2.1 SOFT STOP The SOFT STOP mode has the following features: The CPU can communicate: the system program calls organization...
Page 162 Timer processing in OB 38/39 While OB 38/39 is being executed, the processing of timers and counters is stopped. If necessary, timer information must be processed from system data area RS 96 to RS 99 or with OB 121 or OB 150. CPU 948 Programming Guide 4 - 10 C79000-G8576-C848-04...
Page 163 WARM RESTART of communication Fig. 4-3 Program execution after POWER UP OB 1 Interruption e.g. by STS operation OB 39 Cyclic processing of communication Fig. 4-4 Program execution after a cycle interruption CPU 948 Programming Guide 4 - 11 C79000-G8576-C848-04...
Page 164 BSTACK overflow (STUEB) or bracket counter overflow (KZU), programming errors or device faults; the following LEDs provide further information: - "ADF" LED - "QVZ" LED - "ZYK" LED by the PG function "program test end" on this CPU. CPU 948 Programming Guide 4 - 12 C79000-G8576-C848-04...
Page 165: Hard Stop
LED displays The HARD STOP status can be recognized by the following LEDs on the front panel of the CPU: Status STOP SYSFAULT BASP CPU 948 Programming Guide 4 - 13 C79000-G8576-C848-04...
Page 166: Overall Reset
STOP to RUN and then back to STOP. Note If you do not want to execute the OVERALL RESET you requested, carry out a MANUAL COLD RESTART or MANUAL WARM RESTART. CPU 948 Programming Guide 4 - 14 C79000-G8576-C848-04...
Page 167 Note In contrast to the CPU 946/947, you can also initiate an OVERALL RESET on the CPU 948 in the RUN mode. In this case, the CPU automatically changes to the STOP mode and the OVERALL RESET is then performed.
Page 168: Start-Up Mode
Mode change START-UP is the transition from the STOP mode to the RUN mode. Start-up types The CPU 948 has the following start-up modes: COLD RESTART ( manual or automatic) WARM RESTART (manual or automatic) (You can select the type of start-up with operating elements and by...
Page 169: Manual And Automatic Cold Restart
If the CPU was in the STOP mode when the power was switched off (for example, following an addressing error), an AUTOMATIC COLD RESTART is not permitted. The STOP mode can only be exited in this case with a MANUAL COLD RESTART. CPU 948 Programming Guide 4 - 17 C79000-G8576-C848-04...
Page 170: Manual And Automatic Warm Restart
A MANUAL or AUTOMATIC WARM RESTART is only permitted when • • the user program was not modified during the stop mode • • a COLD RESTART is not necessary for other reasons (refer to Section 4.4.1). CPU 948 Programming Guide 4 - 18 C79000-G8576-C848-04...
Page 171 If there is a power failure on an expansion unit, (PEU signal), the CPU changes to the STOP mode. It remains in this mode until the PEU signal is switched inactive and then performs an AUTOMATIC WARM RESTART or an AUTOMATIC COLD RESTART. CPU 948 Programming Guide 4 - 19 C79000-G8576-C848-04...
Page 172 You can only abort a WARM RESTART after it has started by WARM RESTART changing the mode selector to STOP or by POWER OFF. If you abort the warm restart in this way, both a COLD RESTART or WARM RESTART is then possible. CPU 948 Programming Guide 4 - 20 C79000-G8576-C848-04...
Page 173: Comparison Between Cold Restart And Warm Restart
I/Os entered in it into the PI lists If DB 1 does not exist: enter the modules which actually exist (only digital I/O) into the PI lists IPC flags are ignored CPU 948 Programming Guide 4 - 21 C79000-G8576-C848-04...
Page 174: Retentive Cold Restart
DX 0 block, the system program goes through a RETENTIVE COLD RESTART instead of a WARM RESTART. How this differs from a "normal" COLD RESTART can be seen in the following section. CPU 948 Programming Guide 4 - 22 C79000-G8576-C848-04...
Page 175: Comparison Of Cold Restart And Retentive Cold Restart
I/Os and IPC flags it contains in the PI lists If DB 1 does not exist: enter the existing modules (only digital I/Os) in the PI lists IPC flags are ignored CPU 948 Programming Guide 4 - 23 C79000-G8576-C848-04...
Page 176: User Interfaces For Start-Up
After processing OB 20, the cyclic program begins by calling OB 1. If OB 20 is not loaded, the CPU begins the cyclic program execution immediately after the COLD RESTART is completed (following the system activities). CPU 948 Programming Guide 4 - 24 C79000-G8576-C848-04...
Page 177 COLD RESTART (the CPU resumes program execution with the first STEP 5 statement in OB 1). The signal states of the flags, IPC flags, semaphore and the block address list (DB 0) are retained. CPU 948 Programming Guide 4 - 25 C79000-G8576-C848-04...
Page 178 COLD RESTART (the CPU resumes program execution with the first STEP 5 statement in OB 1). The signal states of the flags, IPC flags, semaphore and the block address list (DB 0) are retained. CPU 948 Programming Guide 4 - 26 C79000-G8576-C848-04...
Page 179: Extended Automatic Warm Restart With The Cpu 948 (Hot Restart)
The "HOT RESTART" mode specified in the IEC 1131 standard, part WARM RESTART with the 1 is also possible in the CPU 948. The "HOT RESTART" is a warm CPU 948 (HOT RESTART) restart controlled by a battery-backed clock (according to IEC 1131).
Page 180: Interruptions During Start-Up
An AUTOMATIC WARM RESTART WARM RESTART is executed (OB 22 is called and processed from the beginning); AUTOMATIC OB 22 no "remaining start-up" is processed WARM RESTART (OB 21 or OB 22 is not resumed). CPU 948 Programming Guide 4 - 28 C79000-G8576-C848-04...
Page 181: Run Mode
• • there are one or more organization blocks serving as user interfaces for each level of program execution. All the processing levels in a CPU 948 can be programmed simultaneously. The levels are called by the system program according to the events that occur and the preset priority (refer to Section 4.2).
Page 182: Cyclic Program Execution
Output process image of the outputs ( PIQ) Update IPC output flags System activities e.g. loading or deleting blocks com pr essing blocks . . . Fig. 4-6 Cyclic program execution CPU 948 Programming Guide 4 - 30 C79000-G8576-C848-04...
Page 183 - PG function (at checkpoints - refer to Chapter 11), • • by the stop command STS (at operation boundaries), • • by a power failure on the central controller or in the expansion unit (at operation boundaries). CPU 948 Programming Guide 4 - 31 C79000-G8576-C848-04...
Page 184: Specifying Time And Interrupt-Driven Program Execution
- PG function (at checkpoints - refer to Chapter 11), • • by the stop command STS (at operation boundaries), • • by a power failure on the central controller or in the expansion unit (at operation boundaries). CPU 948 Programming Guide 4 - 32 C79000-G8576-C848-04...
Page 185 DX 0. With the default setting in DX 0 ("process interrupts via IB 0 = on") the corresponding process interrupts of IB 0 are processed using OB 6 and OB 9 (refer to Section 4.5.4). CPU 948 Programming Guide 4 - 33 C79000-G8576-C848-04...
Page 186 RUN Mode Delayed interrupt With the delayed interrupt of the CPU 948, small time intervals with a resolution of 1 ms can be set. Once the selected time has elapsed, the system program calls OB 6 once. Resolution The delayed interrupt is generated by calling the special function organization block OB 153 (refer to Section 6.14).
Page 187 Clock-controlled interrupt The CPU 948 has a battery-backed clock (central back-up via the power supply of the central controller), which you can set and read out using the STEP 5 program. This clock allows time-controlled execution of a program section.
Page 188 Clock-controlled interrupts are not checked for collisions! • • Note the special functions OB 122 and OB 142 with which you can disable or delay the servicing of clock-controlled interrupts. CPU 948 Programming Guide 4 - 36 C79000-G8576-C848-04...
Page 189 RUN Mode Cyclic timed interrupts On the CPU 948, you can process 9 different time-controlled programs, each being called at a different cyclic interval. Triggering The basic clock pulse for timed interrupt processing is set to 100 ms. Using a special parameter in data block DX 0, you can adjust this in 10 ms where: 01H ≤...
Page 190 Following this, OB 10 is called immediately again. If, however, there are more than three timed interrupts pending for one of the time bases, a collision of timed interrupts error occurs. CPU 948 Programming Guide 4 - 38 C79000-G8576-C848-04...
Page 191 RUN Mode Collision of timed interrupts In the CPU 948 there are two different types of collisions of timed interrupts: Type of error/cause ISTACK ID Reaction of the CPU Timed interrupt queue overflow: In the "ISTACK output" of The system program calls...
Page 192 DX 0 (refer to Chapter 7) for time-controlled program execution: setting the basic clock rate setting the clock distributor, setting priorities relative to interrupt-driven program execution, enabling/disabling timed interrupt processing. CPU 948 Programming Guide 4 - 40 C79000-G8576-C848-04...
Page 193 4.4.4 Interrupt-Driven Program Depending on the selected mode, two different types of interrupt-driven Execution program execution are possible with the CPU 948: • • PROCESS INTERRUPTS via input byte IB 0 (max. 8 interrupts), • • INTERRUPTS via signal lines of the S5 bus (max. 4 interrupts).
Page 194 The PROCESS INTERRUPTS level is only exited when each signal change in input byte IB 0 has been dealt with and the corresponding OB completely processed. Note Process interrupt-driven program execution cannot be interrupted by further process interrupt-driven program execution. CPU 948 Programming Guide 4 - 42 C79000-G8576-C848-04...
Page 195: Appendix
CPU 946/947, you can set "interrupt at block boundaries" or "interrupt at operation boundaries" as the mode in DX 0. Jumper settings for system For interrupt-driven program execution with the CPU 948, there are interrupts four system interrupts available to you:...
Page 196 • • If there are several interrupts pending, the corresponding organization blocks are called according to the order of priority you specify in DX 0 (single priority). You can specify priority levels 1 to 5 for the four interrupts. CPU 948 Programming Guide 4 - 44 C79000-G8576-C848-04...
Page 197 - refer to Section 3.5.4) and only apply to process interrupts via IB 0. Note If a process interrupt is disabled using OB 22 or delayed using OB 142, the RA operation is not effective. CPU 948 Programming Guide 4 - 45 C79000-G8576-C848-04...
Page 198 To avoid double use of flags, you can also use the S flags for most applications. Special "saving" strategies for flags are then no longer necessary, providing the S flags are assigned exclusively to individual program processing levels (there are enough S flags available). CPU 948 Programming Guide 4 - 46 C79000-G8576-C848-04...
Page 199: Interrupt And Error Diagnostics
Error Handling ............5 - 38 CPU 948 Programming Guide...
Page 200 Contents CPU 948 Programming Guide 5 - 2 C79000-G8576-C848-04...
Page 201: Interrupt And Error Diagnostics
At the end of the chapter, you will learn how to activate integrated system functions for a self-test of the CPU 948. CPU 948 Programming Guide 5 - 3...
Page 202: Frequent Errors In The User Program
• • Check to see if all blocks called are actually in the memory. • • If required by other blocks (e.g. standard function blocks), scratchpad flags should be saved by interrupt-driven and time-controlled programs and loaded again when these program sections have been completed. CPU 948 Programming Guide 5 - 4 C79000-G8576-C848-04...
Page 203: Error Information
STOP LED flashes quickly interruptions and errors (see section 4.1). SYS FAULT LED lit continuously ADF LED lit continuously Addressing error QVZ LED lit continuously Timeout error ZYK LED lit continuously Cycle time exceeded error CPU 948 Programming Guide 5 - 5 C79000-G8576-C848-04...
Page 204 CPU went into the STOP mode. Since the BSTACK is filled from the bottom, the top line of the BSTACK display contains the block that called the block containing an error. CPU 948 Programming Guide 5 - 6 C79000-G8576-C848-04...
Page 205 1) The blocks executed before OB 1 are internal blocks belonging to the system program (the BSTACK is structured chronologically). In the example, PB 3 called the faulty block at relative address "00008 - 1 = 00007". During the jump to this faulty block, no data block was open. CPU 948 Programming Guide 5 - 7 C79000-G8576-C848-04...
Page 206: Procedure For Error Analysis
BSTACK display you will find information about the block which called the block causing the error. The system data RS 75 (refer to Section 8.3.4) also contains further detailed error information. CPU 948 Programming Guide 5 - 8 C79000-G8576-C848-04...
Page 207: Control Bits And Interrupt Stack
The text on the screen of your programmer depends on the PG software you are using. It may therefore differ from the display shown here. The description of the screen information is nevertheless relevant. CPU 948 Programming Guide 5 - 9 C79000-G8576-C848-04...
Page 208: Control Bits
The ISTACK screen form shown in Fig. 5-1 reflects the PG software STEP 5/ST, Version 6.3 or STEP 5/MT Version 6.0 with the "Delta diskette CPU 948". In older versions of the PG software, the abbreviations of the control bits may be different.
Page 209 STOP mode caused by STEP 5 operation ’STS’ (after executing an operation) STOPS STOP mode caused by setting the mode selector to the STOP position BEARBE STOP mode after the PROGRAM TEST END programmer function CPU 948 Programming Guide 5 - 11 C79000-G8576-C848-04...
Page 210 COLD RESTART permitted as next start-up type. WIEZU WARM RESTART permitted as next start-up type. URLER Overall reset required. AWEG AUTOMATIC WARM RESTART is preset. ANEG AUTOMATIC COLD RESTART is preset. MSEG Manual start is preset. CPU 948 Programming Guide 5 - 12 C79000-G8576-C848-04...
Page 211 Error in the STEP 5 operations G DB, GX DX QVZNIO QVZ test faulty WEFES Collision of software-driven timed interrupts: queue overflow DB0UN DB 0 has been changed since the last COLD RESTART. Therefore, no WARM RESTART possible. CPU 948 Programming Guide 5 - 13 C79000-G8576-C848-04...
Page 212: Istack Content
0004 0005 ACCU4: 0000 0005 0004 0005 CONDITION CODE: OVFLS ODER OVFL ERAB STATUS CAUSE OF INTERR.: TRAF STUEB STUEU STOP PARE HALT WEFEH Fig. 5-2 Example of a screen page "OUTPUT ISTACK" CPU 948 Programming Guide 5 - 14 C79000-G8576-C848-04...
Page 213 Block stack (BSTACK) pointer: Contains the 20-bit offset address of the last BSTACK entry (always Exxxx). PB-NO Block type and number of the most (depending on type recently processed block PB, OB ...) CPU 948 Programming Guide 5 - 15 C79000-G8576-C848-04...
Page 214 =’ RLO’ (result of logic operation, refer to bit codes), c = 1: ’A(’, c = 0: ’O(’. ACCU1 to Contents of the calculation registers ACCU4 (accumulators) at the time of the interruption CPU 948 Programming Guide 5 - 16 C79000-G8576-C848-04...
Page 215 Parity error (OB 30) Cycle monitoring time exceeded (OB 26) STOP STOP mode caused by setting the mode selector to the STOP position STOP mode caused by STEP 5 operation ’STS’ (after executing an operation) CPU 948 Programming Guide 5 - 17 C79000-G8576-C848-04...
Page 216 OB 22 (AUTOMATIC WARM RESTART). HALT Multiprocessor STOP mode: a) selector switch on the coordinator (COR) is in the STOP position b) another CPU entered the STOP mode in multiprocessing. CPU 948 Programming Guide 5 - 18 C79000-G8576-C848-04...
Page 217: Example Of Error Diagnosis Using The Istack
(= depth 01, with the ID of the ADF). You can page down through the ISTACK until you reach depth 04, first . representing the CYCLE program execution level, which was interrupted CPU 948 Programming Guide 5 - 19 C79000-G8576-C848-04...
Page 218: Error Handling Using Organization Blocks
(process interrupts – QVZ) Timeout during access to the distributed I/O peripherals (extended OB 29 none address area — QVZ) Parity error and timeout in the user memory (PARE) OB 30 STOP CPU 948 Programming Guide 5 - 20 C79000-G8576-C848-04...
Page 219 If, as an exception, you do not want one of these errors to interrupt cyclic program processing (e.g. while putting the system into operation), a block end statement in the appropriate organization block is sufficient. Example of OB 25: ADF occurred Cyclic processing is continued, no CPU STOP CPU 948 Programming Guide 5 - 21 C79000-G8576-C848-04...
Page 220 Note You can nest a maximum of five error organization blocks. With more than 5 errors, the CPU goes into the HARD STOP mode because of ISTACK overflow. CPU 948 Programming Guide 5 - 22 C79000-G8576-C848-04...
Page 221: Causes Of Error And Reactions Of The Cpu
If an error occurs, note the entries in the control bits under "Error IDs" and the entries in the ISTACK under CAUSE OF INTERR. The following sections explain possible causes of error in greater detail. CPU 948 Programming Guide 5 - 23 C79000-G8576-C848-04...
Page 222: Ob 19: Calling A Logic Block That Is Not Loaded (Kb)
You can read system data register RS 75 to determine (via the STEP 5 program) which type of error occurred. The contents of RS 75 are as follows: - for a KB error: 0101H, - for a KDB error: 0904H. CPU 948 Programming Guide 5 - 24 C79000-G8576-C848-04...
Page 223: Ob 23/24, Ob 28/29:Timeout Error (Qvz)
STEP 5 operation which caused the timeout when the program is resumed: extension = "acknowledgement monitoring time + time of error handling in the system program + processing time if error OB is called". CPU 948 Programming Guide 5 - 25 C79000-G8576-C848-04...
Page 224: Ob 25: Addressing Error (Adf)
For bit operations, the bit in the process image is scanned and combined logically or set/reset. Load and transfer operations are also executed. Continued processing can, however, result in incorrect or unwanted reactions. CPU 948 Programming Guide 5 - 26 C79000-G8576-C848-04...
Page 225: Ob 26: Cycle Time Exceeded Error (Zyk)
DX 0 (refer to Chapter 7) or by programming OB 31. The default monitoring time is 200 ms. In the cyclic program, the cycle monitoring time can be retriggered by calling the special function OB 222. CPU 948 Programming Guide 5 - 27 C79000-G8576-C848-04...
Page 226: Ob 27: (Substitution Error Suf)
PARE accessing the If a parity error occurs when accessing the operating system RAM, the operating system RAM system program does not call OB 30, but changes to a HARD STOP. CPU 948 Programming Guide 5 - 28 C79000-G8576-C848-04...
Page 227: Ob 32: Load And Transfer Error (Traf)
When the system program detects a load or transfer error, it calls OB 32, if this is loaded. The operation that caused the load or transfer error is not processed. If OB 32 is not loaded, the CPU changes to the STOP mode. CPU 948 Programming Guide 5 - 29 C79000-G8576-C848-04...
Page 228: Ob 33: Collision Of Timed Interrupts Error (Wefes/Wefeh)
Time-controlled program processing (timed interrupts) is handled by Interrupts Error organization blocks OB 6, OB 9 and OB 10 to OB 18. (WEFES/WEFEH) The following types of timed errors can occur on the CPU 948: Queue overflow Cause: Queue overflow servicing timed interrupts: •...
Page 229 This can increase the cycle time considerably, depending on the duration of error handling by the system program and of processing time of the organization block. CPU 948 Programming Guide 5 - 31 C79000-G8576-C848-04...
Page 230: Ob 34: Error With G Db/Gx Dx (Fedbx)
Error numbers for up to a maximum of three errors can be transferred when OB 35 is called. If there are more than three errors, this is indicated by an overflow identifier. CPU 948 Programming Guide 5 - 32 C79000-G8576-C848-04...
Page 231: Ob 36: Error In Self-Test
(Further Reading /14/). 5.6.12 OB 36: Error in Self-test OB 36 is called if one of the self-test routines detects an error when it is run (for detailed information, refer to Section 5.7). CPU 948 Programming Guide 5 - 33 C79000-G8576-C848-04...
Page 232: Self-Test
Self-Test Self-Test 5.7.1 Overview The CPU 948 contains integrated self-test routines in the system program. Activating/deactivating You can activate or deactivate the functions of the self-test using bits in system data RS 137. Time slice To reduce the cycle load caused by the self-test in the RUN mode, only part of the self-test is carried out within a cycle (time slice).
Page 233: Description Of The Test Functions
Note The user memory test takes time to complete - CPU 948-1 (640 Kbytes) approx. 5 seconds - CPU 948-2 (1 664 Kbytes) approx. 22 seconds Testing the BASP signal (In the STOP mode, without time slice) This test checks whether a BASP signal is output by the CPU. The test function runs in the stop loop.
Page 234 In the code test of the STEP 5 blocks, an error is detected if one or more logic blocks were modified dynamically. It is possible to modify blocks with the PG. If this is the case, the checksum is created by the system program of the CPU 948. CPU 948 Programming Guide 5 - 36...
Page 235: Settings
This means that you can only check the user memory of a newly inserted CPU by activating the test function in RS 137 following an OVERALL RESET and then repeating the OVERALL RESET. CPU 948 Programming Guide 5 - 37 C79000-G8576-C848-04...
Page 236: Error Handling
Errors detected by the self-test component "BASP signal" in the STOP mode are also indicated in RS 75. The following START-UP only leads to cyclic operation if no STP operation is programmed in OB 36. CPU 948 Programming Guide 5 - 38 C79000-G8576-C848-04...
Page 237 RS 76 FFFFH RS 77 FFFFH RS 78 FFFFH Testing cycle time monitoring System data word Error information. RS 75 error no. 6600H RS 76 FFFFH RS 77 FFFFH RS 78 FFFFH CPU 948 Programming Guide 5 - 39 C79000-G8576-C848-04...
Page 238 Testing the block code of STEP 5 logic blocks System data word Error information RS 75 error no. 620AH RS 76 block type/block no. (IDs from block header) RS 77 expected checksum RS 78 actual checksum CPU 948 Programming Guide 5 - 40 C79000-G8576-C848-04...
Page 239: Integrated Special Functions
Ob 180: Variable Data Block Access ........6 - 53 CPU 948 Programming Guide...
Page 240 OB 254/255: Copy/Duplicate Data Blocks ........6 - 65 CPU 948 Programming Guide...
Page 241: Integrated Special Functions
OBs. You will also learn how to recognize errors in the execution of a special function and possible ways of handling them in the program. CPU 948 Programming Guide 6 - 3 C79000-G8576-C848-04...
Page 242: Introduction
Introduction Introduction The operating system of the CPU 948 provides you with special functions which you can call if necessary with a conditional (JC OB x) or an unconditional (JU OB x) block call. Organization blocks OB 100 to 255 are reserved for these special functions.
Page 243 ACCU 1, low word, low byte, 8 bits ACCU-1-LH: ACCU 1, low word, high-byte, 8 bits High word Low word High byte Low byte High byte Low byte 24 23 16 15 CPU 948 Programming Guide 6 - 5 C79000-G8576-C848-04...
Page 244 STEP 5 program using a compare operation and once again program a reaction to an error. Which of the error reactions occurs for the individual special function OBs is explained in the following sections. CPU 948 Programming Guide 6 - 6 C79000-G8576-C848-04...
Page 245 "JC OB 131/132/133" operation does not have the same effect as a "genuine" block change, but functions as a STEP 5 operation without block operand. No interrupts are nested (with the default "interrupts at block boundaries"). CPU 948 Programming Guide 6 - 7 C79000-G8576-C848-04...
Page 246: Ob121: Set/Read System Time
Bit no. 14: 0 = AM with 12 hour format 1 = PM " " 0 in 24 hour format Bit no. 15: 0 = 12 hour format 1 = 24 hour format CPU 948 Programming Guide 6 - 8 C79000-G8576-C848-04...
Page 247 F108H 100th to 10th seconds in the data field unequal to 0. Entries from the 100th to the 10th second must equal 0. F109H Hour format differs from setting in OB 151 CPU 948 Programming Guide 6 - 9 C79000-G8576-C848-04...
Page 248 1: KH = 9555; 2: KH = 1010; 3: KH = 9308; OB 121 transfers the required time parameters from DB 10 to the system data area RS 96 to RS 99. CPU 948 Programming Guide 6 - 10 C79000-G8576-C848-04...
Page 249 3: KH = 9308; 93 years, 8 months It is Tuesday the 10th of August 1993, 15 hours, 57 minutes, 29 seconds and 940 milliseconds (9 tenths and 4 hundredths of a second). CPU 948 Programming Guide 6 - 11 C79000-G8576-C848-04...
Page 250: Ob 122: "Disable Interrupts" On/Off
Interrupts that have already been registered, are then no longer serviced if the mode "interruptability at block boundaries" is set in DX 0. Parameters ACCU-1-L Function no., Permitted values: 1 = disable all interrupts 2 = enable all interrupts CPU 948 Programming Guide 6 - 12 C79000-G8576-C848-04...
Page 251 KB 1 Load function ID in ACCU-1-L OB 122 Disable all interrupts } Critical program section KB 2 Load function ID in ACCU-1-L OB 122 Enable all interrupts CPU 948 Programming Guide 6 - 13 C79000-G8576-C848-04...
Page 252: Ob 124: Delete Step 5 Blocks
While the blocks are actually being deleted, user interrupts are disabled: no interrupts come through. By calling OB 124, the contents of ACCU 1 to ACCU 4 are modified. The BR register is retained. CPU 948 Programming Guide 6 - 14 C79000-G8576-C848-04...
Page 253 Table 6-4 Results bits of OB 124 CC 1 CC 0 Meaning Scan Special function was processed correctly Processing of special function aborted with "warning" Processing of special function aborted with "error" CPU 948 Programming Guide 6 - 15 C79000-G8576-C848-04...
Page 254 Conflict with an online function (except for "compress memory") 10 ms waiting time not elapsed Example KY 6,100 This sequence of operations deletes OB 124 data block DX 100 in the user memory CPU 948 Programming Guide 6 - 16 C79000-G8576-C848-04...
Page 255: Ob 125: Generate Step 5 Blocks
While the blocks are actually being generated, user interrupts are disabled: no interrupts come through. By calling OB 125, the contents of ACCU 1 to ACCU 4 are modified. The BR register is retained. CPU 948 Programming Guide 6 - 17 C79000-G8576-C848-04...
Page 256 Table 6-6 Result bits of OB 125 CC 1 CC 0 Meaning Scan Special function was processed correctly Processing of special function aborted with "warning" Processing of special function aborted with "error" CPU 948 Programming Guide 6 - 18 C79000-G8576-C848-04...
Page 257 10 ms waiting time not yet elapsed Example KF +2000 This sequence of operations KY 5,24 generates DB 24 with a length of OB 125 2000 data words (total length including header: 2005 words) CPU 948 Programming Guide 6 - 19 C79000-G8576-C848-04...
Page 258: Ob 126: Define, Transfer Process Images
Read in the process image of the IPC input flags Output the process image of the IPC output flags Set up system internal address list (analogous to DB 1) (only permitted in COLD RESTART OB 20) CPU 948 Programming Guide 6 - 20 C79000-G8576-C848-04...
Page 259 To set up the address list, you must however call OB 126 for each additional process image using function "5" singly (only in COLD RESTART). 2. ACCU-1-L No. of the flag byte FY n, at which the data field begins permitted values: 0 to 250 CPU 948 Programming Guide 6 - 21 C79000-G8576-C848-04...
Page 260 (wrong DW number) or the address list contains an incorrect ID word Address list number illegal The call for the function is not permitted at the current program execution level CPU 948 Programming Guide 6 - 22 C79000-G8576-C848-04...
Page 261 The address lists with numbers 1 to 4 are only accepted by the CPU using an OB 126 call in OB 20 (COLD RESTART). To do this, OB 126 must be called with function number ’5’ in OB 20. CPU 948 Programming Guide 6 - 23 C79000-G8576-C848-04...
Page 262 KB 1 Transfer address list no. ’1’ FY 51 to FY 51 KB 50 Data field begins with FY 50 OB 126 Call for outputting the PIQ possibly evaluation of status bits CPU 948 Programming Guide 6 - 24 C79000-G8576-C848-04...
Page 263: Ob 129: Battery State
POWER UP lithium cell and accu closed open cyclic lithium cell closed closed cyclic lithium cell and accu Parameters none Result RLO = ’0’: battery OK RLO = ’1’: battery run down CPU 948 Programming Guide 6 - 25 C79000-G8576-C848-04...
Page 264: Ob 131: Delete Accus 1, 2, 3 And 4
ACCUs 1 to 4 extremely simply. OB 131 overwrites all four registers with ’0’. Parameters None Result The ACCUs 1 to 4 (each 32 bit) are deleted (’0’). Possible errors None CPU 948 Programming Guide 6 - 26 C79000-G8576-C848-04...
Page 265: Ob 132/133: Roll-Up Accu/Roll-Down Accu
OB 132 and OB 133. Note With the STEP 5 operations ENT (extended operation set) and TAK (system operation) the ACCU contents can also be shifted (refer to Section 3.4.3). Possible errors None CPU 948 Programming Guide 6 - 27 C79000-G8576-C848-04...
Page 266 ACCU 4 <ACCU 1> <ACCU 3> <ACCU 4> ACCU 3 OB 133 <ACCU 3> ACCU 2 <ACCU 2> <ACCU 2> ACCU 1 <ACCU 1> before after Fig. 6-2 Effect of the "roll-down" function CPU 948 Programming Guide 6 - 28 C79000-G8576-C848-04...
Page 267: 6.10 Ob 141: "Disable Single Cyclic Timed Interrupts" On/Off
8 (OB 17) 11 = ’1’ period 9 (OB 18) 12 to 15 Reserved; these bits must be ’0’ As long as a bit is set to ’1’ the corresponding interrupt is disabled. CPU 948 Programming Guide 6 - 29 C79000-G8576-C848-04...
Page 268 After correct and error-free processing the system program sets the RLO to ’0’. Calling OB 141 has the following results: Contents of ACCU 1 Funct. no. in ACCU-2-L before after control word control word mask control word mask control word CPU 948 Programming Guide 6 - 30 C79000-G8576-C848-04...
Page 269 • • The status of the control word can be scanned with the following Scan control word program sequence: 1. load function no. ’2’ or ’3’ in ACCU-2-L, 2. load value ’0’ in ACCU 1, 3. call OB 141, 4. read out ACCU 1. CPU 948 Programming Guide 6 - 31 C79000-G8576-C848-04...
Page 270: 6.11 Ob 142: "Delay All Interrupts" On/Off
Parameters 1. Control word OB 142 enters the interrupts to be delayed in a system-internal control word, as follows: Bit no. C o n t r o l w o r d CPU 948 Programming Guide 6 - 32 C79000-G8576-C848-04...
Page 271 ACCU 1 are set to ’0’ in the control word. The new control word is loaded in ACCU 1 2b) ACCU 1 New control word or mask depending on the required function. CPU 948 Programming Guide 6 - 33 C79000-G8576-C848-04...
Page 272 The status of the control word can be scanned with the following program sequence: 1. load function no. ’2’ or ’3’ in ACCU-2-L, 2. load value ’0’ in ACCU 1, 3. call OB 142, 4. read out ACCU 1. CPU 948 Programming Guide 6 - 34 C79000-G8576-C848-04...
Page 273: 6.12 Ob 143: "Delay Single Cyclic Timed Interrupts" On/Off
8 (OB 17) 11 = ’1’ period 9 (OB 18) 12 to 15 Reserved, these bits must be ’0’ As long as a bit is set to ’1’, the corresponding interrupt is disabled. CPU 948 Programming Guide 6 - 35 C79000-G8576-C848-04...
Page 274 After correct and error-free processing the system program sets the RLO to ’0’. Calling OB 143 has the following results: Contents of ACCU 1 Funct. no. in ACCU-2-L before after control word control word mask control word mask control word CPU 948 Programming Guide 6 - 36 C79000-G8576-C848-04...
Page 275 • • The status of the control word can be scanned with the following Scan control word program sequence: 1. load function no. ’2’ or ’3’ in ACCU-2-L, 2. load value ’0’ in ACCU 1, 3. call OB 143, 4. read out ACCU 1. CPU 948 Programming Guide 6 - 37 C79000-G8576-C848-04...
Page 276: 6.13 Ob 150: Set/Read System Time
• • Input and output is BCD coded. Function Using OB 150, you can set or read out the date and time of the CPU 948 in your user program. The date and time are known as the "system time".
Page 277 Flag byte x+1 Data field word 2 Flag byte x+2 Flag byte x+3 Data field word 3 Flag byte x+4 Flag byte x+5 Data field word 4 Flag byte x+6 Flag byte x+7 CPU 948 Programming Guide 6 - 39 C79000-G8576-C848-04...
Page 278 The errors listed in the following table may occur. If an error occurs, the system program sets the RLO to ’1’ and stores the error IDs listed in the table in ACCU 1. CPU 948 Programming Guide 6 - 40 C79000-G8576-C848-04...
Page 279 30 = Weekday (3 = Thursday) + bit 0 to 3 = 0 3: KH = 9 3 1 0 93 = Year (BCD) 10 = Month (BCD) Continued on next page CPU 948 Programming Guide 6 - 41 C79000-G8576-C848-04...
Page 280 KH = 2 4 3 0 Day of month = 24 (BCD) Weekday = 3 = Thursday DW 7: KH = 9 3 1 0 Year = 93 (BCD) Month = 10 (BCD) CPU 948 Programming Guide 6 - 42 C79000-G8576-C848-04...
Page 281: 6.14 Ob 151: Set/Read Time For Clock-Controlled Interrupt
6.14 OB 151: Set/Read Time for Clock-Controlled Interrupt Function By calling OB 151 you can do the following: • • cause the CPU 948 to activate the clock-controlled interrupt ("timed job" - OB 9, refer to Section 4.5.3) at a selected time: - every minute...
Page 282 Flag byte x+1 Data field word 2 Flag byte x+2 Flag byte x+3 Data field word 3 Flag byte x+4 Flag byte x+5 Data field word 4 Flag byte x+6 Flag byte x+7 CPU 948 Programming Guide 6 - 44 C79000-G8576-C848-04...
Page 283 There is no point in generating a timed job cyclically (e.g. with an unconditional OB 151 call with function number ’1’ in OB 1). Result After correct processing of OB 151, the RLO, the condition code bits OR, ERAB and OS = 0. CPU 948 Programming Guide 6 - 45 C79000-G8576-C848-04...
Page 284 Job type illegal Note If incorrect parameters are assigned and a valid timed job was previously generated, the error IDs listed above are transferred; the previously generated timed job, however, remains active. CPU 948 Programming Guide 6 - 46 C79000-G8576-C848-04...
Page 285 (= 6), this means that OB 9 is only called every leap year. • • If the value "29", "30" or "31" is selected with the job type "every month" (= 5), OB 9 is only called in the months which have these dates. CPU 948 Programming Guide 6 - 47 C79000-G8576-C848-04...
Page 286 6. "Job yearly, on the 1st of May at 00:01:45": You must specify: Job type 6 (Function no. in ACCU-2-L = 1) Seconds Minutes Format/hour = Day of month= Month Continued on the next page CPU 948 Programming Guide 6 - 48 C79000-G8576-C848-04...
Page 287 If no job is active, you obtain the following result in the data field: Data field word 0: FFFF H Data field word 1: FFFF H Data field word 2: FFF0 H Data field word 3: FFFF H CPU 948 Programming Guide 6 - 49 C79000-G8576-C848-04...
Page 288: 6.15 Ob 153: Set/Read Time For Delayed Interrupt
Permitted values: 0001H to FFFFH b) ACCU-1-L Function no. Permitted values: 1 = define and start delay time 2 = stop delay time (= cancel job) 3 = read remaining delay time CPU 948 Programming Guide 6 - 50 C79000-G8576-C848-04...
Page 289 The STEP 5 operations in OB 22 for calling OB 153: KF +5000 Value for ACCU-2-L: 5000 ms KF +1 Value for ACCU-1-L: function no. = 1 for "define and start delay time" OB 153 Call OB 153 CPU 948 Programming Guide 6 - 51 C79000-G8576-C848-04...
Page 290 STEP 5 operations for calling OB 153: KF +3 Value for ACCU-1-L: function no. = 3 for "read out remaining time" OB 153 Call OB 153 ACCU-1-L contains the time the delay job still has to run. CPU 948 Programming Guide 6 - 52 C79000-G8576-C848-04...
Page 291: 6.16 Ob 180: Variable Data Block Access
ACCU-1-L (the DBA and DBL registers are updated accordingly), • • the RLO is cleared (RLO = 0), • • all other bit and word codes are cleared, • • the content of ACCU-1-L = 0. CPU 948 Programming Guide 6 - 53 C79000-G8576-C848-04...
Page 292 If, on the other hand, the access window is shifted in a called logic block by calling OB 180, when program execution returns from the called block (block end operation), it is returned to the position it had when the nested logic block was called. CPU 948 Programming Guide 6 - 54 C79000-G8576-C848-04...
Page 293 DW 256 and DW 257 using STEP 5 operations. By shifting the DBA resgister by 16, data words 256 and 257 can be addressed as "DW 240" and "DW 241". Continued on next page CPU 948 Programming Guide 6 - 55 C79000-G8576-C848-04...
Page 294 "34" DW 2 4 1542H "35" 4 1543H DW 3 "36" DW 4 4 1544H "37" 4 1545H DW 5 "38" DW 6 4 1545H Fig. 6-3 Shifting the DB start address CPU 948 Programming Guide 6 - 56 C79000-G8576-C848-04...
Page 295: Ob 181: Test Data Blocks (Db/Dx)
OB 181 checks whether a specified data block exists and returns the characteristic parameters of a data block. Parameters ACCU-1-L a) ACCU-1-LL Block number, Permitted values: 1 to 255 b) ACCU-1-LH Block ID, Permitted values: 1 = DB 2 = DX CPU 948 Programming Guide 6 - 57 C79000-G8576-C848-04...
Page 296 It also enters an error ID in ACCU-1-L. Table 6-17 Error codes of OB 181 and their scans RLO CC 1 CC 0 ACCU-1-L Meaning Scan B501H Block does not exist B502H Wrong block number B503H Wrong block ID CPU 948 Programming Guide 6 - 58 C79000-G8576-C848-04...
Page 297: 6.18 Ob 182: Copy Data Area
No. of 1st transferred data word in source DB 3rd word Destination DB type Destination DB no. 4th word No. of 1st transferred data word in the destination DB 5th word No. of data words CPU 948 Programming Guide 6 - 59 C79000-G8576-C848-04...
Page 298 3 = F flag area 4 = S flag area Data block no., Permitted values: 3 to 255 (only with address area type ’1’ or ’2’; with address area type ’3’ or ’4’ irrelevant) CPU 948 Programming Guide 6 - 60 C79000-G8576-C848-04...
Page 299 Length of the destination block in block header < 5 B62AH words "Number of data words to be transmitted" illegal B62BH (= 0 or > 4091) B62CH Source data block too short Destination data block too short CPU 948 Programming Guide 6 - 61 C79000-G8576-C848-04...
Page 300: Ob 202 To 205: Multiprocessor Communication
• • OB 205: receive test The special function organization block OB 205 checks the number of occupied memory fields in the COR C buffer. CPU 948 Programming Guide 6 - 62 C79000-G8576-C848-04...
Page 301: Ob 222: Restart Cycle Monitoring Time
By calling this special function, the maximum permitted cycle time for the current cycle is extended by the value selected at the time of the call. Parameters none Possible errors none CPU 948 Programming Guide 6 - 63 C79000-G8576-C848-04...
Page 302: Ob 223: Compare Start-Up Modes
ID to ACCU-1-LL. Table 6-19 Results IDs of OB 223 in ACCU-1-LL Meaning Start-up modes the same Internal system error Start-up modes not the same Single processor mode, comparison of start-up modes not possible CPU 948 Programming Guide 6 - 64 C79000-G8576-C848-04...
Page 303: Ob 254/255: Copy/Duplicate Data Blocks
Function A data block is copied from the memory card to the user memory and retains its original block number. The start address is entered in the address list in DB 0. CPU 948 Programming Guide 6 - 65 C79000-G8576-C848-04...
Page 304 Number of the block to be duplicated (source). 2. ACCU-1-LH Number of the new block (destination). The following block numbers are possible: Block type Block number DB (OB 255) 3 to 255 DX (OB 254) 3 to 255 CPU 948 Programming Guide 6 - 66 C79000-G8576-C848-04...
Page 305 CC 1 and CC 0. The result can be evaluated by conditional jump operations. Result codes Table 6-20 Result codes for OB 254/255 CC 1 CC 0 Meaning Scan Special function correctly processed Special function aborted with "warning" Special function aborted with "error" CPU 948 Programming Guide 6 - 67 C79000-G8576-C848-04...
Page 306 2. "Duplicate": KY 80,85 This sequence of operations OB 255 duplicates data block DB 85; the new data block has the number 80. The contents of DB 80 and DB 85 are identical. CPU 948 Programming Guide 6 - 68 C79000-G8576-C848-04...
Page 307: Extended Data Block Dx 0
Parameter Assignment using the PG Screen Form ......7 - 14 CPU 948 Programming Guide...
Page 308 Contents CPU 948 Programming Guide 7 - 2 C79000-G8576-C848-04...
Page 309: Extended Data Block Dx 0
You will find information about the meaning of the various DX 0 parameters and will learn how to create and how to assign parameters for a DX 0 data block based on examples. CPU 948 Programming Guide 7 - 3 C79000-G8576-C848-04...
Page 310: Application
"interruptability at block boundaries" and "interruptability at operation boundaries". • • Processing system interrupts: With the CPU 948, you can now also combine "process interrupts via IB 0 = off" (= system interrupt processing) with "interruptability at block boundaries".
Page 311: Structure Of Dx 0
The possible parameters are listed in Section 7.3. The specified numerical values are in hexadecimal format (KH). End ID This indicates the end of DX 0 with EEEEH in the last data word. CPU 948 Programming Guide 7 - 5 C79000-G8576-C848-04...
Page 312 F i eld 2 Par ameter Field ID n Field length n Par ameter F i eld n Par ameter Par ameter DW m End ID Fig. 7-1 Structure of DX 0 CPU 948 Programming Guide 7 - 6 C79000-G8576-C848-04...
Page 313: Example Of Input In Dx 0
• • Close DX 0 after entering the last field with the end identifier "KH=EEEE". CPU 948 Programming Guide 7 - 7 C79000-G8576-C848-04...
Page 314: Parameters For Dx 0
Interrupt servicing: timed interrupts 05xx 1000 000c D Timed interrupt servicing "on" 1001 0000 Timed interrupt servicing "off" c = level priority, permitted values: 1 to 5 D c = 1 (highest level priority) CPU 948 Programming Guide 7 - 8 C79000-G8576-C848-04...
Page 315 D = default with DX 0 not loaded or not present. xx = field length (number of data words occupied by the parameters). 3) With the CPU 948, can also be combined with a system interrupt. Must not be combined with process interrupts via IB 0.
Page 316 (= processing of system interrupts level INTERRUPTS) In this mode, the following default priorities are set: • • timed interrupts: level priority 1 (higher priority) • • system interrupts:level priority 2 (lower priority) CPU 948 Programming Guide 7 - 10 C79000-G8576-C848-04...
Page 317 System interrupt INT A/B/C/D level priority 1 Timed interrupts level priority 2 descending System interrupt INT E level priority 3 priority System interrupt INT F level priority 4 System interrupt INT G level priority 5 CPU 948 Programming Guide 7 - 11 C79000-G8576-C848-04...
Page 318: Examples Of Parameter Assignment
A and B, its green RUN LED lights up immediately following start-up. The BASP signal (disable command output) is, however, only deactivated when all three CPUs have completed their start-up. This means that CPU C cannot access the digital I/Os. CPU 948 Programming Guide 7 - 12 C79000-G8576-C848-04...
Page 319 INT E. Owing to its higher priority, this interrupts timed interrupt servicing, the processing of the delayed interrupt and the processing of a timed job. Under "field length", specify the number of data words occupied by a parameter! CPU 948 Programming Guide 7 - 13 C79000-G8576-C848-04...
Page 320: Parameter Assignment Using The Pg Screen Form
With the PG system software, screen forms are available for assigning using the PG Screen Form parameters in DX 0 for the CPU 948. The PG software automatically generates data block DX 0 according to the default parameters (values in bold face)and parameters you have specified. To assign parameters to DX 0, two screen forms are required.
Page 321 The delayed interrupt and clock-controlled interrupt must, if necessary, be activated extra by switching off process interrupts (interrupt servicing on) 2) CPU 948: System interrupts can be serviced with "interruptability at block boundaries" or "interruptability at operation boundaries" Fig. 7-3...
Page 322 - no timer updating, - cycle monitoring time = 2.5 seconds, - level priority for timed interrupts = 2 - system interrupt INT E with priority = 1 . Continued on the next page CPU 948 Programming Guide 7 - 16 C79000-G8576-C848-04...
Page 323 For the PROCESS INTERRUPTS parameter, select the setting ’no’ with function key F3. • • Press the enter key to confirm your input. Data block DX 0 is then generated by the system software. CPU 948 Programming Guide 7 - 17 C79000-G8576-C848-04...
Page 324 Examples of Parameter Assignment CPU 948 Programming Guide 7 - 18 C79000-G8576-C848-04...
Page 325: Memory Assignment And Memory Organization
User Memory Organization in the CPU 948 ........
Page 326 Contents CPU 948 Programming Guide 8 - 2 C79000-G8576-C848-04...
Page 327: Memory Assignment And Memory Organization
Memory Assignment and Memory Organization You can use this chapter as a reference section to check on the organization of the CPU 948 memory. The chapter also includes important information contained in some of the system data words. CPU 948 Programming Guide...
Page 328: Structure Of The Memory Area
Structure of the Memory Area Structure of the Memory Area The memory of the CPU 948 is essentially divided into the following areas: Table 8-1 Structure of the memory area Memory area Data width Location User memory for: OBs, FBs, FXs, PBs, SBs, DBs, DXs...
Page 329: Memory Assignment In The Cpu 948
• • the CPU 948-1 with 640 Kbytes of user memory • • the CPU 948-2 with 1664 Kbytes of user memory. Fig. 8-1 illustrates the distribution of the address area of the CPU 948 and the location of the user memory versions.
Page 330: Memory Assignment For The System Ram
Memory Assignment in the CPU 948 8.2.1 Memory Assignment for the System RAM Bit no.: Address: D 0000H System program and system data E 9FFFH E A000H S flags E AFFFH E B000H System program data E DEAFH E DEB1H...
Page 331 Memory Assignment in the CPU 948 Bit no.: Address: E F000H RS Area (System Data, 256 Words) Reserved E F200H RT Area (Extended System Data, 256 Words) Reserved E F400H RI Area (Serial Comm. Interface, 256 Words) Reserved E F600H RJ Area (Extended Serial Comm.
Page 332: Memory Assignment For The Peripherals
Memory Assignment in the CPU 948 8.2.2 Memory Assignment for the Peripherals Bit no.: Address: F 0000H Unassigned Peripheral Address Space (52K Words) F D000H reserved F F000H Digital Peripherals (with PI, 128 I/128 Q) P area F F080H Analog Peripherals...
Page 333 Memory Assignment in the CPU 948 Address Areas for Peripherals and Programming Them Area Referenced with Parameter (absolute address) L IB / T IB to 127 E FE00 L IW / T IW to 126 (Process image input) L ID / T ID...
Page 334: User Memory Organization In The Cpu 948
Location of blocks in the In the CPU 948, blocks are stored so that data word DW 0 or the first user memory STEP 5 statement of each block is located at a paragraph address.
Page 335 User Memory Organization in the CPU 948 Example Block List in DB 0 Memory Bit no. Bit no. Header 1 xxxx0H Start Block 1 Body 1 Filler Block Ascending Header 2 Addresses xxxx0H Body 2 Start Block n Header n...
Page 336: Block Headers In User Memory
User Memory Organization in the CPU 948 8.3.1 Block Headers in Each block in the memory begins with a header that is five words User Memory long. The block header is divided as follows: 1st word: Block start ID: 7070H...
Page 337: Block Address List In Data Block Db 0
User Memory Organization in the CPU 948 8.3.2 Block Address List in Data block DB 0 is located in the system RAM of the CPU (beginning Data Block DB 0 at address E E200H). It contains a list with the start addresses of all blocks in the user memory of the CPU.
Page 338: Ri/Rj Area
User Memory Organization in the CPU 948 Example of how to obtain a block address The block start addresses of the program blocks are located in DB 0 and begin at address E E400H. The start address of PB 22 can therefore be read out by accessing memory at address E E416H (= start address of the PB + 16H).
Page 339: Rs/Rt Area
1. you do not use standard FBs 2. you do not use PG functions via SINEC H1 and the parallel S5 bus. Only an overall reset can clear the RS/RT areas. CPU 948 Programming Guide 8 - 15 C79000-G8576-C848-04...
Page 340 60 to 63 Available to user E F03FH 64 to 67 System program E F044H 68 to 71 Error address with QVZ and PARE errors E F047H 72 to 74 System program CPU 948 Programming Guide 8 - 16 C79000-G8576-C848-04...
Page 341 As a supplement to the listing above, the following pages provide the bit assignments of a few system data registers that you can evaluate via STEP 5 operations or with your programmer (see Section 5.4 for information on the abbreviations). CPU 948 Programming Guide 8 - 17 C79000-G8576-C848-04...
Page 342: Bit Assignment Of The System Data Words
Status of I 0.7 Status of I 0.6 Status of I 0.5 Status of I 0.4 Status of I 0.3 Status of I 0.2 Status of I 0.1 Status of I 0.0 CPU 948 Programming Guide 8 - 18 C79000-G8576-C848-04...
Page 343 Bit = ’1’: edge I 0.5 Bit = ’1’: edge I 0.4 Bit = ’1’: edge I 0.3 Bit = ’1’: edge I 0.2 Bit = ’1’: edge I 0.1 Bit = ’1’: edge I 0.0 CPU 948 Programming Guide 8 - 19 C79000-G8576-C848-04...
Page 344 Example Bit no. 15 14 13 12 11 10 9 Value The time of the last cycle is as follows: 10 ms = (16 + 8) 10 ms = 240 ms CPU 948 Programming Guide 8 - 20 C79000-G8576-C848-04...
Page 345 Interruption by programming error (UPROG – cold restart) "End of program test" (BEARBE) Stop switch (STOPS) End of operation stop (STS) End of cycle stop (STP) Multiprocessing stop (HALT) PG stop (PGSTP) CPU 948 Programming Guide 8 - 21 C79000-G8576-C848-04...
Page 346 WARM RESTART executed (WIEDF) Low byte COLD RESTART executed (NEUDF) Automatic start after NAU Manual start COLD RESTART WITH MEMORY PG overall reset PG system start PG warm restart PG cold restart CPU 948 Programming Guide 8 - 22 C79000-G8576-C848-04...
Page 347 If errors appear during update of the process image input/output tables or interprocessor communication flags, the corresponding bits are set to ’1’. – The system data words RS 17 to 47 are structured analogous to RS 16. CPU 948 Programming Guide 8 - 23 C79000-G8576-C848-04...
Page 348 RS 68 QVZ error addr. high E F044H RS 69 QVZ error addr. low E F045H RS 70 PARE error addr. high E F046H RS 71 PARE error addr. low E F047H CPU 948 Programming Guide 8 - 24 C79000-G8576-C848-04...
Page 349 00H to 10H exist. The structure of the parameter field is described later. The two following tables list the error groups "general errors" and "errors in DX 0 or DB 0". CPU 948 Programming Guide 8 - 25 C79000-G8576-C848-04...
Page 350 RUN/STOP switch set to STOP position Halt signal from the coordinator Not used Load/transfer error with L BY/T BY (process image update) Load/transfer error during addressing via the BR register I/Os not ready Timeout/parity error during initialization CPU 948 Programming Guide 8 - 26 C79000-G8576-C848-04...
Page 351 Error in DX 0 block ID Error in DX 0 parameter Errors in DB 1 No DB 1 in multiprocessing Invalid DB 1 header DB 1 ID set more than once DB 1 byte offset without ID CPU 948 Programming Guide 8 - 27 C79000-G8576-C848-04...
Page 352 Address decoder error Error testing the user memory organized in words Error testing the user memory organized in bytes Error testing cycle time monitoring Error testing the BASP signal Error testing the hardware clock CPU 948 Programming Guide 8 - 28 C79000-G8576-C848-04...
Page 353 Parameter 1 block ID or code word in DX 0 or DB 1 Parameter 2 incorrect parameter 1 in DX 0 or DB 1 (FFFFH: parameter irrelevant) Parameter 3 incorrect parameter 2 in DX 0 or DB 1 (FFFFH: parameter irrelevant) CPU 948 Programming Guide 8 - 29 C79000-G8576-C848-04...
Page 354 Parameter 3 error address low with address code error, actual checksum low when testing the system program code Parameter 1 check pattern when testing the user memory Parameter 2 error address high Parameter 3 error address low CPU 948 Programming Guide 8 - 30 C79000-G8576-C848-04...
Page 355 RS 78, parameter 3 = 0078H: Data block length = 120 data words Information contained in the message: In the STEP 5 user program, data block DX 100 should be generated with a length of 120 data words. However, this already exists. CPU 948 Programming Guide 8 - 31 C79000-G8576-C848-04...
Page 356 Structure of RS 96 (real-time clock: seconds, 1/100 seconds) High byte Bit no. Assignment Seconds, tens, permitted: 00H to 05H Seconds, units, permitted: 00H to 09H Low byte 1/10 second, permitted: 00H to 09H 1/100 second, permitted: 00H to 09H CPU 948 Programming Guide 8 - 32 C79000-G8576-C848-04...
Page 357 Structure of RS 98 (real-time clock: date, day of the week) High byte Bit no. Assignment Date, tens, permitted: 00H to 03H Date, units, permitted: 00H to 09H Low byte Day of the week, permitted: 00H to 06H for Mon. to Sun. CPU 948 Programming Guide 8 - 33 C79000-G8576-C848-04...
Page 358 Structure of RS 99 (real-time clock: year, month) High byte Bit no. Assignment Year, tens, permitted: 00H to 09H Year, units, permitted: 00H to 09H Low byte Month, tens, permitted: 00/01H Month, units, permitted: 00 to 09H CPU 948 Programming Guide 8 - 34 C79000-G8576-C848-04...
Page 359 • • by the STEP 5 program or • • with a PG job "output address". Note When you first receive your CPU and following an overall reset, the password is deleted and the software protection switched off. CPU 948 Programming Guide 8 - 35 C79000-G8576-C848-04...
Page 360 Bit nos. 0 to 7 of a 14-bit password Processing a request does not depend on OB 38 or OB 39 being loaded. This means that software protection can be activated in the STOP mode. CPU 948 Programming Guide 8 - 36 C79000-G8576-C848-04...
Page 361 Low byte 1 = no password active 1 = deleting not possible, wrong password 1 = software protection (password) already activated 1 = illegal password 1 = error counter overflow CPU 948 Programming Guide 8 - 37 C79000-G8576-C848-04...
Page 362 The block is entered (block does not yet exist) Overwrite block Message "Block exists"; after confirming with the enter key (block already exists) the message "Block type and number wrong" is displayed. CPU 948 Programming Guide 8 - 38 C79000-G8576-C848-04...
Page 363 3. Wait at least as long as the cycle time of OB 39 or OB 1. 4. Output the address E F078H again. 5. Enter the new password "1234H" by overwriting the content with the hexadecimal number D234H. CPU 948 Programming Guide 8 - 39 C79000-G8576-C848-04...
Page 364 Low byte Test address lines Not used Code test of the STEP 5 logic blocks in the user memory Not used Not used Code test of the system program Not used Not used CPU 948 Programming Guide 8 - 40 C79000-G8576-C848-04...
Page 365 (IM number 8) reserved (IM number 7) reserved (IM number 6) reserved (IM number 5) reserved (IM number 4) reserved (IM number 3) reserved (IM number 2) reserved (IM number 1) CPU 948 Programming Guide 8 - 41 C79000-G8576-C848-04...
Page 366: Addressable System Data Area
’C’ ’P’ E 8203H ’U’ ’9’ E 8204H ’4’ ’8’ E 8205H ’V’ ’x’ E 8206H ’.’ ’y’ E 8207H E 820BH For ’x’ and ’y’ the current version number is entered. CPU 948 Programming Guide 8 - 42 C79000-G8576-C848-04...
Page 367 You can also use the SYSTEM PARAMETER PG online function to find the information contained in a few system data registers (e.g., concerning the internal structure of the CPU, the software version, the CPU ID). CPU 948 Programming Guide 8 - 43 C79000-G8576-C848-04...
Page 368 Slot ID CPU 3 Slot ID CPU 2 Slot ID CPU 1 Low byte CPU type: 0010 = CPU 948 (only valid in conjunction with the CPU ID) CPU-ID 2: 1000 = S5-155U CPU 948 Programming Guide 8 - 44...
Page 369 Addressable System Data Area Word 21 Bit no. High byte reserved Bit no. Low byte Release of the PG interface software in the form "xyH" Example: 13H corresponds to release "V1.3" CPU 948 Programming Guide 8 - 45 C79000-G8576-C848-04...
Page 370 Addressable System Data Area CPU 948 Programming Guide 8 - 46 C79000-G8576-C848-04...
Page 371: Memory Access Using Absolute Addresses
Accessing the Dual-Port RAM Memory ........9 - 29 CPU 948 Programming Guide...
Page 372 Contents CPU 948 Programming Guide 9 - 2 C79000-G8576-C848-04...
Page 373: Memory Access Using Absolute Addresses
Memory Access Using Absolute Addresses This chapter explains how to use STEP 5 operations and special STEP 5 registers to address data in certain memory areas using absolute addresses. CPU 948 Programming Guide 9 - 3 C79000-G8576-C848-04...
Page 374: Introduction
• • Words: Each address addresses a 16-bit word (= 2 bytes). Organization of the local memory is fixed (see Chapter 8) Organization of the global memory depends on the type of modules that are plugged into the programmable controller: CPU 948 Programming Guide 9 - 4 C79000-G8576-C848-04...
Page 375 E FFFFH F EFFFH F F000H F F400H F FC00H Pages F FE00H 1024 byte/words F FEFFH 2048 byte/words F FFFFH Page address register (select register) Fig. 9-1 Global and local memory CPU 948 Programming Guide 9 - 5 C79000-G8576-C848-04...
Page 376 LY CB, LY CW, LY CD, TY CB, TY CW, TY CD, TSC, • • Section of the global area organized in words (addresses F F400H to F FBFFH, = dual-port RAM area) with: LW CW, LW CD, TW CW, TW CD, TSC CPU 948 Programming Guide 9 - 6 C79000-G8576-C848-04...
Page 377 LY CB, LY CW, LY CD, f) LW CW, LW CD, TY CB, TY CW, TY CD, (TSC) TW CW, TW CD, (TSC) Fig. 9-2 Access to local or global areas using absolute addresses CPU 948 Programming Guide 9 - 7 C79000-G8576-C848-04...
Page 378: Memory Access Via Address In Accu 1
20 19 16 15 Address bits Address bits 0 to 15 16 to 19 The following pages explain which registers you can use with the operations. Examples explain how to use the operations. CPU 948 Programming Guide 9 - 8 C79000-G8576-C848-04...
Page 379: Lir/Tir: Loading To Or Transferring From A 16-Bit Memory Area Indirectly
Loading the contents of an addressed memory register into register ’0’or ’1 overwrites the address stored in ACCU 1. Registers 4, 7, 13, 14 and 15 do not exist on the CPU 948. LIR/TIR operations with these register numbers must not be used.
Page 380 LIR/TIR with 16-bit memory areas (word-oriented) addressed Register n memory location ACCU 1 LIR n addressed Register n memory location ACCU 1 TIR n Fig. 9-4 LIR/TIR with 8-bit memory areas (byte-oriented) CPU 948 Programming Guide 9 - 10 C79000-G8576-C848-04...
Page 381 The DBA register remains the same if one of the following occurs: • • a jump operation (JU/JC) causes program processing to continue in a different block, • • the CPU activates a different program processing level. CPU 948 Programming Guide 9 - 11 C79000-G8576-C848-04...
Page 382 When DX 17 is called, the address of the memory word in which DW 0 is 152H. stored is entered in the DBA register. In this example, the DBA is Note: In the ISTACK, the address entered in the DBA register appears under the heading ’DB-ADD’. CPU 948 Programming Guide 9 - 12 C79000-G8576-C848-04...
Page 383 DBL register and vice-versa. This would mean that transfer error monitoring is no longer guaranteed. On the CPU 948, changes in the DBA/DBL registers are undone, as soon as the current block is completed (BSTACK entries). Manipulations on the DBA/DBL registers are therefore only effective in the block in which they were made.
Page 384 When DX 17 is called, the number of existing data words is entered in the 8 (DW 0 to DW 7) DBL register. In this example the DBL is Note: In the ISTACK, the number entered in the DBL register appears under the heading "DBL-REG". CPU 948 Programming Guide 9 - 14 C79000-G8576-C848-04...
Page 385: Examples Of Access To Dw > 255
ACCU 1: address of the data word to be written to last ACCU 2: address of the data word to be written to ACCU 3: constant Continued on the next page CPU 948 Programming Guide 9 - 15 C79000-G8576-C848-04...
Page 386 (if not, return to the loop) 0038 0039 WEIT Continue the program ... 003A after all DWs have been written to ... 003B 003C :BEU 003D 003E NIVO If DB 100 does not exist 003F CPU 948 Programming Guide 9 - 16 C79000-G8576-C848-04...
Page 387: Ldi/Tdi: Loading To Or Transferring From A 32-Bit Memory Area Indirectly
LDI/TDI: Loading to or The following table shows which register names you can use on the Transferring from a 32-Bit CPU 948 for the LDI and TDI operations and how these are assigned. Memory Area Indirectly Table 9-3 32-bit register for LDI/TDI...
Page 388 Load address of flag byte FY 0 :TDI A2 Store content of ACCU 2 E FC00 = 34 (The values ’12H’ and ’56H’ from E FC01 = 78 ACCU 2 are lost) CPU 948 Programming Guide 9 - 18 C79000-G8576-C848-04...
Page 389: Transferring Memory Blocks
Table 9-5 and cannot overlap. Permitted memory areas Table 9-5 Memory areas permitted for TNW, TXB and TXW Addresses Memory area User memory: 0 0000H to C FFFFH 16-bit area (dependent on memory configuration) CPU 948 Programming Guide 9 - 19 C79000-G8576-C848-04...
Page 390 If a timeout (QVZ) occurs during the transfer, the operation is interrupted and the appropriate error OB called. The error address is the address at which an error occurred (refer to Section 5.6.3). CPU 948 Programming Guide 9 - 20 C79000-G8576-C848-04...
Page 391 :TXB Transferring bytes 1 to 6 from a 16-bit to an 8-bit area: <field length in words> e.g. KH 0003 <source address> DH EF008 :ENT :ENT <destination address> DH EFC10 :TXW :TXW CPU 948 Programming Guide 9 - 21 C79000-G8576-C848-04...
Page 392: Operations With The Base Address Register (Br Register)
• • The BR register is retained after nesting in a different program execution level. • • If a different program execution level is called by the system program, the BR register is set to ’0’. CPU 948 Programming Guide 9 - 22 C79000-G8576-C848-04...
Page 393: Operations For Transfer Between Registers
Transfer the contents of the base address register (20 bits) to the STEP address counter (20 bits) Bits 2 to 2 are set to ’0’. The following figure illustrates how the registers are changed by the operations. CPU 948 Programming Guide 9 - 23 C79000-G8576-C848-04...
Page 394: Accessing The Local Memory
ACCU 1 Constant add the specified constant to content (-32768 to of the BR register and transfer the +32767) content of ACCU-1-L to the word addressed in this way CPU 948 Programming Guide 9 - 24 C79000-G8576-C848-04...
Page 395: Accessing The Global Memory
The TSG operation enables testing and setting of "occupied" registers. Operation Operand Description -32768 to Add the specified constant to the content +32767 of the BR register and test and set the location addressed in this way. CPU 948 Programming Guide 9 - 25 C79000-G8576-C848-04...
Page 396 CPU detects a transfer error (TRAF) and calls OB 32. If OB 32 is not loaded, the CPU changes to the STOP mode with the error code TRAF (ISTACK). CPU 948 Programming Guide 9 - 26 C79000-G8576-C848-04...
Page 397 • • between F 0000H and F FFFFH (LY GB, TY GB), • • between F 0000H and F FFFEH (LY GW, TY GW) • • between F 0000H and F FFFCH (LY GD, TY GD). CPU 948 Programming Guide 9 - 27 C79000-G8576-C848-04...
Page 398 (TRAF) and calls OB 32. ACCU 1 contains the error ID 1A01H. If OB 32 is not loaded, the CPU changes to the STOP mode with the error code TRAF (ISTACK). CPU 948 Programming Guide 9 - 28 C79000-G8576-C848-04...
Page 399: Accessing The Dual-Port Ram Memory
• • If the page register is changed in a block, its value is retained when the program returns to the calling block at the end of the block. • • The page register is retained after nesting in another program execution level. CPU 948 Programming Guide 9 - 29 C79000-G8576-C848-04...
Page 400 "occupied" register. If the low byte contains ’0’, the TSC operation enters the slot ID of the CPU in the "occupied" register. Testing (reading) and possible occupation (writing) form a program unit that cannot be interrupted. CPU 948 Programming Guide 9 - 30 C79000-G8576-C848-04...
Page 401 ACCU-1-L LY CD -32768 to add the specified constant to content +32767 of the BR register and load the double word addressed in this way in the open page into ACCU 1 CPU 948 Programming Guide 9 - 31 C79000-G8576-C848-04...
Page 402 If the absolute addresses are not in the range shown, the CPU detects a load/transfer error (TRAF) and calls OB 32. If OB 32 is not loaded, the CPU changes to the STOP mode with the error bit TRAF (ISTACK). CPU 948 Programming Guide 9 - 32 C79000-G8576-C848-04...
Page 403 If the absolute addresses are not in the range shown, the system program detects a load/transfer error (TRAF) and calls OB 32. If OB 32 is not loaded, the CPU changes to the STOP mode with the error bit TRAF (ISTACK). CPU 948 Programming Guide 9 - 33 C79000-G8576-C848-04...
Page 404 Operations with the Base Address Register (BR Register) CPU 948 Programming Guide 9 - 34 C79000-G8576-C848-04...
Page 405: Multiprocessor Mode And Com Munication In The S5-155U
Output Parameters............10 - 38 CPU 948 Programming Guide...
Page 406 Extending the IPC Flag Area ..........10 - 66 CPU 948 Programming Guide...
Page 407: Multiprocessor Mode And Communication In The S5-155U
(Section 10.1). The second part of the chapter provides you with detailed instructions and examples of exchanging larger amounts of data in the multiprocessor mode (multiprocessor communication Sections 10.2 to 10.9). CPU 948 Programming Guide 10 - 3 C79000-G8576-C848-04...
Page 408: Multiprocessor Mode
(CPs). • • For the exchange of large amounts of data (e.g., entire data blocks) between the CPU 948, CPU 946/947, CPU 928B, CPU 928 and CPU 922 you are supported by the "special functions for multiprocessing" OB 200 to OB 205 (for more information refer to Section 10.2).
Page 409: Exchanging Data Via Ipc Flags
CPU and never read out and vice-versa. Memory area With the CPU 948 the memory area for the IPC flags in the coordinator and the CPs covers the addresses F F200H to F F2FFH. On a CPU/communications processor there are 256 available IPC flag bytes.
Page 410 CPU, you can use them as normal flags! In DB 1, indicate only the number of IPC flag bytes that you actually need: the smaller the number of IPC flag bytes, the shorter the transfer time! CPU 948 Programming Guide 10 - 6 C79000-G8576-C848-04...
Page 411 IPC input flags: FY 192 to FY 223 CP 1: FY 120 to FY 125 CP 2 CP 2: FY 195 to FY 200 Fig. 10-2 Example of IPC flag areas on the CPs CPU 948 Programming Guide 10 - 7 C79000-G8576-C848-04...
Page 412: Exchanging Data Via Handling Blocks
Exchanging Data via Handling blocks are capable of multiprocessing. A special parameter Handling Blocks assignment for the multiprocessor mode is not necessary. For more information on handling blocks refer to the appropriate manual. CPU 948 Programming Guide 10 - 8 C79000-G8576-C848-04...
Page 413: What Needs To Be Programmed For The Multiprocessor Mode?
Using the DB 1 screen form 1. Select the editor for the DB 1 screen form on your PG (refer to Fig. 10-3). 2. Enter the required values for "digital inputs" etc. as decimal numbers. CPU 948 Programming Guide 10 - 9 C79000-G8576-C848-04...
Page 414 1. Write the DB 1 start ID in data words 0, 1 and 2: DW 0: KH = 4D41 (’M’ ’A’) DW 1: KH = 534B (’S’ ’K’) DW 2: KH = 3031 (’0’ ’1’) CPU 948 Programming Guide 10 - 10 C79000-G8576-C848-04...
Page 415 Flag byte 60 KH = CA00; ID word for IPC flag outputs KF = +00070; Flag byte 70 KF = +00072; KF = +00100; Flag byte 100 KH = EEEE; End ID CPU 948 Programming Guide 10 - 11 C79000-G8576-C848-04...
Page 416 Direct transfer to byte addresses >127 is possible regardless of the entries in DB 1. Direct transfer of byte addresses of the extended I/Os (T OY, T OW) is also possible regardless of the entries in DB 1. CPU 948 Programming Guide 10 - 12 C79000-G8576-C848-04...
Page 417: Starting Up In The Multiprocessor Mode
OB 20, OB 21 and OB 22 appropriately. You can call special function block OB 223 to check whether the start-up types of all the CPUs are the same (refer to Chapter 6). CPU 948 Programming Guide 10 - 13 C79000-G8576-C848-04...
Page 418: Test Mode
Since no CPU can output the BASP signal in case of an error in the test mode, the test mode must be switched inactive after successful installation to avoid a critical or even dangerous situation arising in the system. CPU 948 Programming Guide 10 - 14 C79000-G8576-C848-04...
Page 419: Multiprocessor Communication
RECEIVE functions is normally 32 words. If the block length (without header) is not a multiple of 32 words, the last field of data to be transferred is an exception and is less than 32 words long. CPU 948 Programming Guide 10 - 15 C79000-G8576-C848-04...
Page 420: How The Transmitter And Receiver Are Identified
The CPUs are numbered so that the leftmost CPU has the number 1 and each subsequent CPU to the right has a number increased by 1. Example S5-135U/155U: Fig. 10-4 Sender/receiver identification CPU 948 Programming Guide 10 - 16 C79000-G8576-C848-04...
Page 421: Why Data Is Buffered
RECEI V E , p a r a m e t e r o f t r a n s m i t t i n g CPU = 3 When CPU 2 is ready to receive, it copies the data from the coordinator buffer to the destination DB. CPU 948 Programming Guide 10 - 17 C79000-G8576-C848-04...
Page 422: How The Buffer Is Processed And Managed
The receiving capacity indicates how many of the memory fields reserved for a link are occupied at any particular time. The sum of the transmitting and receiving capacity is always equal to the number of memory fields reserved for a link. CPU 948 Programming Guide 10 - 18 C79000-G8576-C848-04...
Page 423 In the example, fields H and I are received while fields K and L are sent. The example illustrates the queue organization of the buffer: the fields of data sent first (A,B,C...) are received first (A,B,C...). CPU 948 Programming Guide 10 - 19 C79000-G8576-C848-04...
Page 424 The capacity of the buffer is insufficient to compensate tempo- rary imbalances in the frequency with which the CPUs trans- mit and receive data. CPU 948 Programming Guide 10 - 20 C79000-G8576-C848-04...
Page 425: System Start-Up
On completion of the WARM RESTART, i.e. in the RUN mode, the user program is not processed from the start, but from the point at which it was interrupted. The point of interruption can, for example, be within the SEND function. CPU 948 Programming Guide 10 - 21 C79000-G8576-C848-04...
Page 426: Calling Communication Obs
The communication OBs do not require a working area (for buffering variables) and do not call data blocks. They do, of course, access areas containing parameters, although only the parameters marked as output parameters are modified. CPU 948 Programming Guide 10 - 22 C79000-G8576-C848-04...
Page 427: How To Assign Parameters To Communication Obs
You can assign a flag area with 10 flag bytes for all communications functions. The functions themselves require different numbers of bytes. Refer to the description of the single functions (Section 10.4ff). CPU 948 Programming Guide 10 - 23 C79000-G8576-C848-04...
Page 428: How To Evaluate The Output Parameters
• • the OV and OS bits (word condition codes) are always cleared, • • the OR, STA, ERAB bits (bit condition codes) are always cleared, • • RLO, CC 1 and CC 0 indicate whether a function has been executed correctly and completely. CPU 948 Programming Guide 10 - 24 C79000-G8576-C848-04...
Page 429 Condition code byte Bit no. Number W = 1: Warning E = 1: Error I = 1: Initialization conflict Number: - of a warning - of an error - of an initialization conflict CPU 948 Programming Guide 10 - 25 C79000-G8576-C848-04...
Page 430 Errors are detected and indicated in the ascending order of the error numbers. This means that several errors may have occurred although (currently) only one is indicated. The other errors are then indicated by further calls. CPU 948 Programming Guide 10 - 26 C79000-G8576-C848-04...
Page 431 The parameter "block number " is incorrect, since the data block does not exist. The parameter "start address of the assignment list" is too high or the data block is too short. CPU 948 Programming Guide 10 - 27 C79000-G8576-C848-04...
Page 432 CPU in a lower processing level (i.e. cyclic program execution). - The CPU’s own number is incorrect (system data corrupted); following power down/power up the CPU number is generated again by the system program. CPU 948 Programming Guide 10 - 28 C79000-G8576-C848-04...
Page 433 The parameter "field number" (SEND) is incorrect. The data block is too short or the field number too high. The data block is not large enough to receive the data field transmitted by the sender (RECEIVE). CPU 948 Programming Guide 10 - 29 C79000-G8576-C848-04...
Page 434 The SEND function cannot transfer data, since the transmitting capacity was already zero when the function was called. The RECEIVE function cannot accept data, since the receiving capacity was already zero when the function was called. CPU 948 Programming Guide 10 - 30 C79000-G8576-C848-04...
Page 435: Runtimes Of The Communication Obs
The runtimes listed in table 10-6 assume that of four CPUs inserted in a rack, only the CPU whose runtimes are being measured accesses the SIMATIC S5 bus. If other CPUs use the bus intensively, the runtime increases particularly for the send/receive functions. CPU 948 Programming Guide 10 - 31 C79000-G8576-C848-04...
Page 436 The length of time that the data are "in transit" is largely dependent on the length of time that the data is buffered and therefore on the structure of the user program (see "Buffering Data"). CPU 948 Programming Guide 10 - 32 C79000-G8576-C848-04...
Page 437: Initialize Function (Ob 200)
If you are using two CPUs, there are two links (transfer directions, "channels"): CPU 1 CPU 2 If you are using three CPUs, there are six links: CPU 1 CPU 2 CPU 3 CPU 948 Programming Guide 10 - 33 C79000-G8576-C848-04...
Page 438 If the INITIALIZE function is called several times, one after the other, the last assignment made is valid. While a CPU is processing the INITIALIZE function, no other multiprocessor communication functions including the INITIALIZE function can be called on other CPUs. CPU 948 Programming Guide 10 - 34 C79000-G8576-C848-04...
Page 439: Call Parameters
"automatic" mode. With the "automatic" setting, the memory fields are divided evenly according to the number of CPUs. Number of Number of Memory fields per CPUs links link 0; 1; 5 to 255 Illegal, causes an initialization conflict CPU 948 Programming Guide 10 - 35 C79000-G8576-C848-04...
Page 440 As the address of the assignment list, specify the data word number at which the assignment list begins in flag bytes FY x+4 (high byte) and FY x+5 (low byte). CPU 948 Programming Guide 10 - 36 C79000-G8576-C848-04...
Page 441 48 must be inserted depending on the number of assigned memory fields. The sum of these numbers must not exceed 48. Note You must keep to the structure shown in table 10-7 even if you have less than four CPUs. CPU 948 Programming Guide 10 - 37 C79000-G8576-C848-04...
Page 442: Output Parameters
If an initialization conflict occurs, you must change the program/parameters. All the numbers listed in Table 10-3 can occur in the condition code byte. CPU 948 Programming Guide 10 - 38 C79000-G8576-C848-04...
Page 443 In the "automatic" mode, this parameter always has the value 48. In the "manual" mode, it can have a value less than 48. This means that existing memory capacity is not used. CPU 948 Programming Guide 10 - 39 C79000-G8576-C848-04...
Page 444: Send Function (Ob 202)
ACCU-1-LL: 0 to 246 10.5.3 Input Parameters Receiving CPU CPU number of the receiver (destination); the permitted value is between 1 and 4 but must be different from the CPU’s own number. CPU 948 Programming Guide 10 - 40 C79000-G8576-C848-04...
Page 445 DW 64 DW 95 DW 96 DW 127 DW 128 DW 159 DW 160 DW 191 DW 192 DW 223 DW 224 DW 255 DW 256 DW 287 DW 288 DW 319 CPU 948 Programming Guide 10 - 41 C79000-G8576-C848-04...
Page 446: Output Parameters
Incorrect parameter assignment 10.5.4 Output Parameters Condition code byte This byte informs you whether the SEND function was executed correctly and completely. Initialization conflict Has no significance with the SEND function. CPU 948 Programming Guide 10 - 42 C79000-G8576-C848-04...
Page 447 - If the block ID = 2 : DX 0 The parameter "block number" is incorrect. The specified data block does not exist. The parameter "field number" is incorrect. The data block is too short or the field number too high. CPU 948 Programming Guide 10 - 43 C79000-G8576-C848-04...
Page 448 The SEND function cannot transfer data, since the transmitting capacity was already zero when the function was called. Transmitting capacity The "transmitting capacity" indicates how many data fileds can still be sent and buffered. CPU 948 Programming Guide 10 - 44 C79000-G8576-C848-04...
Page 449: Send Test Function (Ob 203)
The CPU’s own number and the number of the receiving CPU identify the link for which the transmitting capacity is determined. 10.6.4 Output Parameters Condition code byte This byte indicates whether the SEND TEST function was executed correctly and completely. CPU 948 Programming Guide 10 - 45 C79000-G8576-C848-04...
Page 450 923C again using the INITIALIZE function. Warning The "warning" number group cannot occur with the SEND TEST function. Transmitting capacity The "transmitting capacity" parameter indicates how many data fields can be sent and buffered. CPU 948 Programming Guide 10 - 46 C79000-G8576-C848-04...
Page 451: Receive Function (Ob 204)
The receive block receives data supplied by the transmitting CPU. Specify the number of the transmitting CPU. The permitted value is between 1 and 4, but must be different from the CPU’s own number. CPU 948 Programming Guide 10 - 47 C79000-G8576-C848-04...
Page 452: Output Parameters
923C again using the INITIALIZE function. The block identifiers supplied by the transmitter are illegal. The following errors are possible: - The block ID is less than 1, - The block ID is greater than 2. CPU 948 Programming Guide 10 - 48 C79000-G8576-C848-04...
Page 453 The RECEIVE function cannot receive data, since the receiving capacity was already zero when the function was called. Receiving capacity The "receiving capacity" parameter indicates how many data fields are still buffered and can still be received. CPU 948 Programming Guide 10 - 49 C79000-G8576-C848-04...
Page 454 Note The difference between the addresses of the first and last data word transferred is a maximum of 31, since a maximum of 32 data words can be transferred per function call. CPU 948 Programming Guide 10 - 50 C79000-G8576-C848-04...
Page 455: Receive Test Function (Ob 205)
10.8.4 Output Parameters Condition code byte This byte indicates whether the RECEIVE TEST function was executed correctly and completely. Initialization conflict Has no significance with the RECEIVE TEST function. CPU 948 Programming Guide 10 - 51 C79000-G8576-C848-04...
Page 456 923C again using the INITIALIZE function. Warning The "warning" number group cannot occur with the RECEIVE TEST function. Receiving capacity The "receiving capacity" parameter indicates how many data fields can be received and buffered. CPU 948 Programming Guide 10 - 52 C79000-G8576-C848-04...
Page 457: 10.9 Applications
The flag area from FY 246 to maximum FY 255 is used by the function blocks as a parameter field for the special function organization blocks. The exact significance of the input and output parameters is explained in the description of the special function organization blocks. CPU 948 Programming Guide 10 - 53 C79000-G8576-C848-04...
Page 458 STAS Start address of the assignment list FW 250 INIC Initialization conflict FY 252 TCAP Total capacity FY 253 Continued on the next page CPU 948 Programming Guide 10 - 54 C79000-G8576-C848-04...
Page 459 Start address of the assignment list 001E FW 250 001F 0020 KB 246 SF OB: OB 200 "Initialize 0021 " 0022 0023 FY 252 Initialization conflict 0024 =INIC 0025 FY 253 Total capacity 0026 =TCAP 0027 CPU 948 Programming Guide 10 - 55 C79000-G8576-C848-04...
Page 460 Field number 0019 FY 249 001A 001B KB 246 SF OB: OB 202 "Send a data field" 001C 001D 001E FY 250 Error/warning 001F =ERWA 0020 FY 251 Transmitting capacity 0021 =TCAP 0022 CPU 948 Programming Guide 10 - 56 C79000-G8576-C848-04...
Page 461 Receiving CPU 000F FY 246 0010 0011 KB 246 SF OB: OB 203 "Test transmitting capacity" 0012 0013 0014 FY 248 Error 0015 =ERRO 0016 FY 249 Transmitting capacity 0017 =TCAP 0018 CPU 948 Programming Guide 10 - 57 C79000-G8576-C848-04...
Page 462 STAA Address of the first received data word FW 252 (start address) ENDA Address of the last received data word FW 254 (end address) Continued on the next page CPU 948 Programming Guide 10 - 58 C79000-G8576-C848-04...
Page 463 FB 205: Testing the receiving capacity FB 205 RECV-TST TCPU ERRO RCAP Parameter Significance Parameter Data Parameter name type type field TCPU Transmitting CPU FY 246 ERRO Error FY 248 RCAP Receiving capacity FY 249 CPU 948 Programming Guide 10 - 59 C79000-G8576-C848-04...
Page 464: Transferring Data Blocks
If the output parameter REST is zero after the transfer, this means that the function block TRANDAT was able to send all the data fields (according to the NUMB parameter). Continued on the next page CPU 948 Programming Guide 10 - 60 C79000-G8576-C848-04...
Page 465 This is necessary to allow various data blocks to be transferred simultaneously. Implementation FB 110 TRAN-DAT STAR ERRO RCPU REST TNDB CUBN NUMB EDGF FIRB Continued on the next page CPU 948 Programming Guide 10 - 61 C79000-G8576-C848-04...
Page 466 I/Q/D/B/T/C: Q BI/BY/W/D: BY DECL :EDGF I/Q/D/B/T/C: Q BI/BY/W/D: BI 0020 =RCPU Assign parameter field for 0021 FY 246 SF OB 202 0022 =TNDB 0023 FW 247 0024 Continued on the next page CPU 948 Programming Guide 10 - 62 C79000-G8576-C848-04...
Page 467 KB 0 RLO = 0, ERRO = 0 004D =ERRO 004E 004F 0050 ERRO :T =ERRO Program end if error: 0051 KB 0 0052 =REST RLO = 1, ERRO contains error number 0053 CPU 948 Programming Guide 10 - 63 C79000-G8576-C848-04...
Page 468 .. from data block DB 3 0003 FW 1 0004 KB 4 .. four data fields 0005 FY 3 0006 KB 2 .. send from 2nd data field 0007 FY 4 0008 Continued on the next page CPU 948 Programming Guide 10 - 64 C79000-G8576-C848-04...
Page 469 Abort after error 0030 :BEU 0031 0032 HALT : 0033 The error handling takes place here 0034 (e.g. stop, message output 0035 on the printer, ...) 0036 00xx Continued on the next page CPU 948 Programming Guide 10 - 65 C79000-G8576-C848-04...
Page 470: Extending The Ipc Flag Area
"normal" flag bytes. To transfer a data record (several bytes) other mechanisms are also required (semaphore variable or DX 0 parameter assignment "transfer IPC flags as a block") are necessary to prevent the receiver from receiving a fragmented data record. CPU 948 Programming Guide 10 - 66 C79000-G8576-C848-04...
Page 471 CPU. • • If a receive data block is longer than the received data word area, the excess data words can be used in the corresponding CPU. CPU 948 Programming Guide 10 - 67 C79000-G8576-C848-04...
Page 472 DW 28 to ..CPU 1 DW 13 DW 29 ... CPU 2 DW 14 DW 30 ... CPU 3 DW 15 DW 31 Refer to the example on the following page CPU 948 Programming Guide 10 - 68 C79000-G8576-C848-04...
Page 473 INITIALIZE function (OB 200). Within the data block, sub-list 2 must occupy data words 0 to 15 and sub-list 2 data words 16 to 31. You must not alter the entries shown in bold face. CPU 948 Programming Guide 10 - 69 C79000-G8576-C848-04...
Page 474 OB 202 to OB 205 are not called in any of the CPUs. The function blocks SEND-DAT and RECV-DAT contain the special function organization blocks for multiprocessor communication OB 202 to OB 205. You cannot call these organization blocks outside SEND-DAT/RECV-DAT. CPU 948 Programming Guide 10 - 70 C79000-G8576-C848-04...
Page 475 KS = S1 evalu- = 1,... ated by ... Maximum three input and DB yyy three output blocks or/and DX zzz Fig. 10-6 Overview of the blocks required in each CPU CPU 948 Programming Guide 10 - 71 C79000-G8576-C848-04...
Page 476 CPUN = CPUN - 1 000C KB 1 Error if: 000D 000E =ERWA CPU no. <1 000F KB 3 0010 :>F 0011 =ERWA CPU no. >4 0012 :TAK Continued on the next page CPU 948 Programming Guide 10 - 72 C79000-G8576-C848-04...
Page 477 0040 0041 FY 249 Field no. = field no. + 1 0042 0043 FY 249 All data fields transferred? 0044 FY 239 0045 :<F 0046 =TRAN 0047 Continued on the next page CPU 948 Programming Guide 10 - 73 C79000-G8576-C848-04...
Page 478 CPUN Number of the CPU, on which FB 101 is called. The numbers 1 to 4 are permitted. ERWA Error/warning (see RECEIVE function / OB 204) Continued on the next page CPU 948 Programming Guide 10 - 74 C79000-G8576-C848-04...
Page 479 :SRW 002F 0030 FY 246 0031 0032 KB 246 SF OB: OB 205 "Test receiving capacity" 0033 0034 FY 248 0035 = OBER Abort if error 0036 Continued on the next page CPU 948 Programming Guide 10 - 75 C79000-G8576-C848-04...
Page 480 004C =ERWA RLO = 0, ERWA = 0 004D :BEU 004E 004F ERWA :L KB 16 Program end if error: 0050 OBER :T =ERWA RLO = 1, ERWA contains 0051 error/warning number CPU 948 Programming Guide 10 - 76 C79000-G8576-C848-04...
Page 481 Function block FB 1 is the interface for the cyclic user program on all three CPUs. CPU 1 calls the INITIALIZE function (OB 200) during the cold restart. The link list is in data block DB 100. Continued on the next page CPU 948 Programming Guide 10 - 77 C79000-G8576-C848-04...
Page 482 KY = 000,000; KS = ’S3’; KY = 000,000; KY = 000,000; KY = 000,000; KS = ’S4’; KY = 000,000; KY = 000,000; KY = 000,000; Continued on the next page CPU 948 Programming Guide 10 - 78 C79000-G8576-C848-04...
Page 483 000F 0010 The error handling routine 0011 is inserted here if an 0012 initialization clonflict 0013 occurs (e.g. stop, output 0014 message on printer, or ...) 00xx Continued on the next page CPU 948 Programming Guide 10 - 79 C79000-G8576-C848-04...
Page 484 0018 ERWA : Run an error handling routine 0019 following an error/warning (here, 001A the error handling routine is 001B inserted, e.g. stop, output error message on printer or screen, or ..) 001C 00xx CPU 948 Programming Guide 10 - 80 C79000-G8576-C848-04...
Page 485: Pg Interfaces And Functions
Condition Codes Indicating Problems ........11 - 35 CPU 948 Programming Guide...
Page 486 Contents CPU 948 Programming Guide 11 - 2 C79000-G8576-C848-04...
Page 487: Pg Interfaces And Functions
PG Interfaces and Functions This chapter explains how to connect your PG to the CPU 948 and the functions provided by the PG software with which you can test your STEP 5 program. If you only use the standard PG interface (1st serial PG interface) you do not need to read Sections 11.4 and 11.5.
Page 488: Overview
• • link via the serial standard interface "PG - PLC", • • link via the 2nd serial interface of the CPU 948, • • link via the S5 bus with SINEC H1.
Page 489: Pg Functions
PG. Checkpoint The PG functions are performed at defined checkpoints in the CPU. In the CPU 948 there are four different checkpoints. Each of these checkpoints has certain test functions assigned to it. Checkpoint "Stop" You can access PG functions that are permissible only in the STOP mode at checkpoint "stop"...
Page 490: Info
: 315664 Words OUTP ADDR MEM CONF SYSPAR BSTACK ISTACK RETURN 1) corresponds to the memory configuration of the CPU 948-1: 320 Kw = 640 Kbytes Fig. 11-1 PG display of the memory configuration CPU 948 Programming Guide 11 - 6 C79000-G8576-C848-04...
Page 491: Installation
Output DIR If you want to display a list of all the programmed blocks on the PG with the CPU 948, OB 0 is displayed instead of the system program blocks. The function is permitted in the operating modes RUN, SOFT STOP, HARD STOP and can also be called within the "program test"...
Page 492: Program Test
You can call the START PG function in the multiprocessor mode to select the restart type you want for all the CPUs you are using. After that, you can start the programmable controller with the last CPU. CPU 948 Programming Guide 11 - 8 C79000-G8576-C848-04...
Page 493 DO FW or DO DW, the message "Statement not processed" appears on the PG. Remedy: Avoid positioning the cursor on the operation following DO FW or DO DW. CPU 948 Programming Guide 11 - 9 C79000-G8576-C848-04...
Page 494 When the "program test" function is active, the cursor cannot be moved beyond the operation following DO FW/DO DW. Remedy: Cancel the function, skip the sequence of operations mentioned above and set a new breakpoint after the operation following DO FW/DO DW CPU 948 Programming Guide 11 - 10 C79000-G8576-C848-04...
Page 495 Afterwards a COLD RESTART is required. The function is also aborted if an interface error occurs during the "program test" function (i.e., the cable between the PG and the programmable controller is disconnected). CPU 948 Programming Guide 11 - 11 C79000-G8576-C848-04...
Page 496 (e.g., you can look at a QVZ error OB directly after an operation that triggers a QVZ error). CPU 948 Programming Guide 11 - 12 C79000-G8576-C848-04...
Page 497 Output ISTACK Output BSTACK Load block Read block Delete block Output block list Force variables Force In rare situations, the function may be terminated and the CPU is subsequently in the STOP mode. CPU 948 Programming Guide 11 - 13 C79000-G8576-C848-04...
Page 498 (i.e., the value 0 is written to each address). While the peripherals are being cleared, this function cannot be interrupted. If any timeout signals (QVZs) occur while the outputs are being cleared, they are ignored. CPU 948 Programming Guide 11 - 14 C79000-G8576-C848-04...
Page 499 Note The PG forces process variables in bytes. If you are forcing several operands, the bytes are changed in memory one after the other distributed over several cycles. CPU 948 Programming Guide 11 - 15 C79000-G8576-C848-04...
Page 500: Serial Link Pg - Plc Via 1St Or 2Nd Serial Interface
135U/155U /2/. • • Link to the PG via SINEC H1/L2/L1 and "swing cable"; the COR C or PG multiplexer can be connected in the link. CPU 948 Programming Guide 11 - 16 C79000-G8576-C848-04...
Page 501: Parallel Operation Of Two Serial Pg Interfaces
Parallel Operation of Two Serial PG Interfaces 11.4 Parallel Operation of Two Serial PG Interfaces You can use the second interface on the CPU 948 (SI 2) as a PG interface in exactly the same way as the first interface.
Page 502 Fig. 11-4 First example of a configuration CPU 948 SI 1 OP connected directly (for operation and monitoring) SI 2 PG connected directly (for programming) Fig. 11-5 Second example of a configuration CPU 948 Programming Guide 11 - 18 C79000-G8576-C848-04...
Page 503: Installation
Parallel Operation of Two Serial PG Interfaces 11.4.1 Installation To use the second interface of the CPU 948 as a PG interface, follow the steps outlined below: Step Action Install the PG submodule in the CPU 948. (refer to the instructions in the Appendix) Connect the PG to the serial interface SI2.
Page 504 The same error message or "Overflow in data exchange with PG" appears if the CPU 948 is currently processing functions of the other PG, which prevent your PG accessing the CPU within the monitoring time. Your input is then rejected. Repeat your input once the functions are completed on the other PG.
Page 505: Sequence In Certain Operating Situations
CPU, the jobs will be processed in the order in which they arrive. The situation may, however, arise that the CPU 948 either receives two jobs simultaneously or receives a job from the second PG while a job from the first PG is still active.
Page 506 Job sent by PG 2 is processed PG 1 must wait until the CPU is free. PG 2 job complete PG 1 requests the current data. Fig. 11-7 Typical sequence of a cyclic function and parallel short-running function CPU 948 Programming Guide 11 - 22 C79000-G8576-C848-04...
Page 507 With both PGs working simultaneously, the sequence shown in figure 11.8 results. This also applies when cyclic functions are active on both PGs; the two PGs then access the PLC alternately. CPU 948 Programming Guide 11 - 23 C79000-G8576-C848-04...
Page 508 Second job sent by PG 2 is processed PG 1 must wait until the CPU is free. Second job of PG 2 complete Fig. 11-8 Sequence of two parallel cyclic functions CPU 948 Programming Guide 11 - 24 C79000-G8576-C848-04...
Page 509 Parallel Operation of Two Serial PG Interfaces Special feature with cyclic If the interrupting function blocks the CPU 948 ("status" in a block functions on both PGs that is not executed) the interrupted function is also blocked. It can only be resumed when the interrupting function is terminated.
Page 510 If "status variables", "force variables" (with the status display) or "status" is output on one interface and "compress memory", "delete block" or "transfer block" on the other, the status display can be corrupted. CPU 948 Programming Guide 11 - 26 C79000-G8576-C848-04...
Page 511: Pg Functions Via The S5 Bus
SINEC H1 using the PG 7xx. With the PG functions via the S5 bus, the CPU 948 can be loaded up to eight times faster than via the PG interface. The actual speed depends on the length of the blocks to be transferred.
Page 512 CPU functions via the S5 bus. Technical requirements The PG functions via the S5 bus with the CPU 948 can only be used when the PG and PLC are networked via SINEC H1. You require the following: • • a PG 7xx with SINEC-H1 connection and with STEP 5 software version 6.3 (ST) or 6.0 (MT) installed with the delta diskette...
Page 513: How The Pg Functions Work Via The S5 Bus
Remember, however, the special features listed in Section 11.5.3. The pages for PG functions are used by the CP 143 and the CPU 948 for the PG functions via the S5 bus and are therefore no longer available for communication via handling blocks.
Page 514 The interface numbers 232ff and 236ff must not be assigned on the CP 143 when operating with other SIMATIC CPUs. When operating the CPU 948 with other CPs, the use of interface numbers 232 to 247 is restricted. Multiprocessor mode The PG functions via the S5 bus can also be used in the multiprocessor mode with the CPU 948.
Page 515: Installation And Getting Started
HDB SYNCHRON (FB 125). The mode selector on the CPU must, however, be set to RUN. An "empty" CPU 948 can be started up via the S5 bus without an OVERALL RESET. After POWER UP, the CPU 948 automatically synchronizes the pages assigned to it on the CP 143 for PG functions via the S5 bus.
Page 516 Edit the path to the CPU 948 in the bus selection screen form of STEP 5. Select the path to the CPU 948 via SINEC H1/CP 143 in the presets screen form of STEP 5. Once these actions have been performed, the PG functions can be used via the S5 bus.
Page 517 The following diagram illustrates how the PG functions via the S5 bus communication via handling use the pages of the CP 143. The free pages for user HDBs can be blocks used by CPUs 1 to 4 for communication via SINEC H1. CPU 948 Programming Guide 11 - 33 C79000-G8576-C848-04...
Page 518 Communication via user HDB with CPU 3 and CPU 4 is not possible. Fig. 11-12 Paths between the PG and CPU 948 and assignment of the CP 143 pages Special features when By synchronizing the CP 143 for communication (FB 125 called with...
Page 519: Condition Codes Indicating Problems
PG Functions via the S5 Bus 11.5.4 Condition Codes Indicating Each of the maximum four CPUs (CPU 948), for which the PG Problems functions via the S5 bus are activated, writes condition codes to its RS and RT areas if an error occurs in the PG functions via the S5 bus.
Page 520 If the pages for PG functions exist and the connection to the CP 143 is established, an information field consisting of 16 words is set up in the RT area of the CPU 948 with the structure shown below. Note As long as there is no connection to the CP 143 (PAFE = 71), e.g.
Page 521 Data transfer complete 1: error Job complete with error Job complete without error 0: SEND enabled 1: SEND disabled 0: RECEIVE disabled 1: RECEIVE enabled Specifically for PG functions via the S5 bus CPU 948 Programming Guide 11 - 37 C79000-G8576-C848-04...
Page 522 PG Functions via the S5 Bus CPU 948 Programming Guide 11 - 38 C79000-G8576-C848-04...
Page 523 Appendix 3: Technical Data of the CPU 948 and CPU 928B ......
Page 524 Contents CPU 948 Programming Guide 12 - 2 C79000-G8576-C848-04...
Page 525 Appendix This chapter provides additional information about the CPU 948 such as jumper settings for system interrupts, notes on inserting and removing the PG submodule, comparisons of runtimes with CPU 946/947 and CPU 928B, and results IDs of some of the special function OBs .
Page 526 Appendix 1: Jumper Settings for System Interrupts Appendix 1: Jumper Settings for System Interrupts For interrupt-controlled program execution with the CPU 948, there are four system interrupts available, as follows: INT A/B/C/D (dependent on the CPU slot, see System Manual /2/,...
Page 527 (components in the same direction as those of the CPU). Secure the submodule with the two screws previously used for the cover. Insert the CPU in the central controller. Switch on the power supply to your PLC again. CPU 948 Programming Guide 12 - 5 C79000-G8576-C848-04...
Page 528 Switch the power supply to your PLC on again. Note Screwing the interface submodule to the CPU diverts disturbance pulses via the screen of the CPU. The CPU must only be operated with the submodule receptacle closed (cover or submodule). CPU 948 Programming Guide 12 - 6 C79000-G8576-C848-04...
Page 529 Appendix 3: Technical Data of the CPU 948 and CPU 928B Appendix 3: Technical Data of the CPU 948 and CPU 928B Operation / Processing CPU 948 CPU 928B Typical command execution times for bit commands: with 0.18 µ s 0.57 µ...
Page 530 Appendix 3: Technical Data of the CPU 948 and CPU 928B Operation / Processing CPU 948 CPU 928B Time-driven program execution 310 µ s for the 1st timed Cycle time extension from nesting an empty OB 13 287 µ s (without STEP 5 operations) at a block boundary int.
Page 531 The function cannot be called at the current program execution level OB 223 Start-up modes same Internal system error Start-up modes not same Single processor mode, no comparison of start-up modes possible CPU 948 Programming Guide 12 - 9 C79000-G8576-C848-04...
Page 532 Destination data block already exists in user memory Online function COMPRESS MEMORY active No memory card inserted Warnings: Conflict with an online function (except COMPRESS MEMORY) 10-ms waiting time not yet elapsed CPU 948 Programming Guide 12 - 10 C79000-G8576-C848-04...
Page 533 Minutes specified in data field illegal 9627H Seconds specified in data field illegal 9628H 1/100 seconds in data field not 0 9629H Hour format not as in OB 151 the incorrect value is in ACCU-2-L CPU 948 Programming Guide 12 - 11 C79000-G8576-C848-04...
Page 534 The shift number is too high; the block end is exceeded by the new window position. b) The shift number is negative. B501H OB 181 Block does not exist B502H Wrong block number B503H Wrong block ID CPU 948 Programming Guide 12 - 12 C79000-G8576-C848-04...
Page 535 Day of week illegal F105H Hours illegal F106H Minutes illegal F107H Seconds illegal F108H 1/100 to1/10 seconds illegal F109H Hour format not as in OB 151 F001H OB 122 Illegal function no. CPU 948 Programming Guide 12 - 13 C79000-G8576-C848-04...
Page 536 Appendix 4: Results IDs of some of the Special Function OBs in ACCU 1 CPU 948 Programming Guide 12 - 14 C79000-G8576-C848-04...
Page 537: Indexes
List of Key Words........... . Index - 1 CPU 948 Programming Guide...
Page 538 Contents CPU 948 Programming Guide 13 - 2 C79000-G8576-C848-04...
Page 539 (in register 8) extended data block EPROM erasable programmable read only memory ERAB first scan (bit code) expansion unit function block extended function block interface module (system)interrupt intelligent peripheral module ISTACK interrupt stack CPU 948 Programming Guide A - 1 C79000-G8576-C848-04...
Page 540 (bit code) statement list stop statement substitution error STUEB BSTACK overflow STUEU ISTACK overflow TRAF transfer or load error cycle error CPU 948 Programming Guide A - 2 C79000-G8576-C848-04...
Page 541 (DB/DX) see results codes copying from memory card 6-65 copying/duplicating 6-65 checkpoints 11-5 general 2-13, 2-35 clock-controlled interrupt 4-33, 4-35, 6-43 generating 3-33 clock-controlled interrupts 4-29 programming 2-37 structure 2-35 CPU 948 Programming Guide Index - 1 C79000-G8576-C848-04...
Page 542 2-23, 2-33 LED display 4-12 - 4-13 structure 2-24 library number 2-36 load operations 3-21, 3-55 local memory access 9-24 general global memory logic operations 3-50 access 9-25 general GRAPH 5 CPU 948 Programming Guide Index - 2 C79000-G8576-C848-04...
Page 543 2-20 1-18 special function organization blocks STEP 5 1-18 OS (overflow latching) programming language SCL 1-18 see results codes programming tools 1-18 OV (overflow) see results codes OVERALL RESET 4-14 CPU 948 Programming Guide Index - 3 C79000-G8576-C848-04...
Page 544 ERAB 3-16, 3-20 sub-level CC 1 and CC 0 3-18, 3-61 SUF (substitution error) 5-28 3-17 suitability of the CPU 948 3-17 supplementary operations 3-17 system data 8-15 2-7, 3-17, 3-20 system data words 3-17, 3-20 bit assignment...
Page 545 4-38 user memory 1-14, 3-10 user program 1-7, 1-9 processing 3-4, 3-11 see program storing 1-10 tasks WARM RESTART 4-21 WEFES/WEFEH (collision of timed interrupts) 5-30 ZYK (cycle time error) 5-27 CPU 948 Programming Guide Index - 5 C79000-G8576-C848-04...
Page 546 List of Key Words CPU 948 Programming Guide Index - 6 C79000-G8576-C848-04...
Page 547 Please check any industry that applies to you: Automotive Pharmaceutical Chemical Plastic Electrical Machinery Pulp and Paper Food Textiles Instrument and Control Transportation Nonelectrical Machinery Other _ _ _ _ _ _ _ _ _ _ _ Petrochemical CPU 948 Programming Guide C79000-G8576-C848-04...
Page 548 Your comments and recommendations will help us to improve the quality and usefulness of our publications. Please take the first available opportunity to fill out this questionnaire and return it to Siemens. Please give each of the following questions your own personal mark within the range from 1 (very good) to 5 (poor).

Siemens CPU 948 Programming Manual

1 Introduction

Contents of Chapter 1

2 User Program

3 Program Execution

4 Operating Statuses and Program Execution Levels

12 Appendix

5 Interrupt and Error Diagnostics

6 Integrated Special Functions

7 Extended Data Block DX 0

8 Memory Assignment and Memory Organization

9 Memory Access Using Absolute Addresses

Introduction

10 Multiprocessor Mode

11 PG Interfaces and Functions

13 Indexes

Quick Links

Related Manuals for Siemens CPU 948

Summary of Contents for Siemens CPU 948