Processor Reset# Signal; Figure 30. Voltage Translation Circuit; Figure 31. Processor Reset# Signal Routing Topology With No Itp700Flex Connector - Intel 852GM Design Manual

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Figure 30. Voltage Translation Circuit

5.6.

Processor RESET# Signal

The RESET# signal is a common clock signal driven by the GMCH CPURST# pin. In a production
system where no ITP700FLEX debug port is implemented, a simple point-to-point connection between
the CPURST# pin of the GMCH and processor RESET# pin is recommended (see Figure 31). On-die
termination of the AGTL+ buffers on both the processor and the GMCH provide proper signal quality
for this connection. This is the same case as for the other common clock signals listed Section 5.3.
Length L1 of this interconnect should be limited to minimum of 1 inch and maximum of 6.5 inches.

Figure 31. Processor RESET# Signal Routing Topology with NO ITP700FLEX Connector

For a system that implements an ITP700FLEX debug port a more elaborate topology is required in order
to guarantee proper signal quality at both the processor signal pad and the ITP700FLEX input receiver.
In this case the topology illustrated in Figure 32 should be implemented. The CPURST# signal from the
GMCH should fork out (do not route one trace from GMCH pin and then T-split) towards the
processor's RESET# pin as well as towards the Rtt and Rs resistive termination network placed next to
the ITP700FLEX debug port connector. Rtt (54.9 Ω + 1%) pulls-up to the VCCP voltage and is placed
at the end of the L2 line that is limited to a 12-inch maximum length. Rs (22.6 Ω +/- 1%) should be
placed right next to Rtt to minimize the routing between them in the vicinity of the ITP700FLEX
connector to limit the L3 length to less than 0.5 inches. ITP700FLEX operation requires the matching of
L2 + L3 - L1 length to the length of the BPM[4:0]# signals length within ± 250 mils. See Table 28 for
routing length summary and termination resistor values.
®
Intel 852GM Chipset Platform Design Guide
1.3K ohm
330 ohm
+/- 5%
From Driver
Rs
CPU
Intel Celeron M Processor Front Side Bus Design Guidelines
3.3V
330 ohm
+/- 5%
R1
+/- 5%
Q2
Q1
3904
L1
3.3V
R2
To Receiver
3904
GMCH
71