Control Signals - Scke[3:0], Scs#[3:0]; Table 23. Control Signal To So-Dimm Mapping - Intel 852GME Design Manual

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6.3.3. Control Signals – SCKE[3:0], SCS#[3:0]
The GMCH/MCH control signals, SCKE[3:0] and SCS#[3:0], are clocked into the DDR SDRAM
devices using clock signals SCK/SCK#[5:0]. The GMCH/MCH drives the control and clock signals
together, with the clocks crossing in the valid control window. The GMCH/MCH provides one chip
select (CS) and one clock enable (CKE) signal per SO-DIMM physical device row. Two chip select and
two clock enable signals will be routed to each SO-DIMM. Refer to Table 23 for the CKE and CS#
signal to SO-DIMM mapping.

Table 23. Control Signal to SO-DIMM Mapping

Signal
SCS#[0]
SCS#[1]
SCS#[2]
SCS#[3]
SCKE[0]
SCKE[1]
SCKE[2]
SCKE[3]
The control signal routing should transition from an external layer to an internal signal layer under the
GMCH/MCH, keep to the same internal layer until transitioning back out to an external layer to connect
to the appropriate pad of the SO-DIMM connector and the parallel termination resistor. If the layout
requires additional routing before the termination resistor, return to the same internal layer and transition
back out to an external layer immediately prior to parallel termination resistor.
External trace lengths should be minimized. Intel suggests that the parallel termination be placed on both
sides of the board to simplify routing and minimize trace lengths. All internal and external signals
should be ground reference to keep the path of return current continuous. Intel suggests that all control
signals be routed on the same internal layer.
Resistor packs are acceptable for the parallel (Rt) control termination resistors, but control signals can
not be placed within the same R pack as the data or command signals. Figure 27 and Table 24 below
depict the recommended topology and layout routing guidelines for the DDR-SDRAM control signals.
® ®
Intel 852GME, Intel 852GMV and Intel
System Memory Design Guidelines (DDR-SDRAM)
Relative To SO-DIMM Pin
SO-DIMM0 AD23
SO-DIMM0 AD26
SO-DIMM1 AC22
SO-DIMM1 AC25
SO-DIMM0 AC7
SO-DIMM0 AB7
SO-DIMM1 AC9
SO-DIMM1 AC10
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852PM Chipset Platforms Design Guide
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