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SYSTEM BUS OVERVIEW
The square and circle symbols are used in the timing diagrams to indicate the clock in which
particular signals of interest are driven and sampled. The square indicates that a signal is
driven (asserted, initiated) in that clock. The circle indicates that a signal is sampled
(observed, latched) in that clock.
Signals that are driven in the same clock by multiple System bus agents exhibit a "wired-OR
glitch" on the electrical-low-to-electrical-high transition. To account for this situation, these
signal state transitions are specified to have two clocks of settling time when deasserted
before they can be safely observed. The bus signals that must meet this criteria are: BINIT#,
HIT#, HITM#, BNR#, AERR#, BERR#.
3.2.
SIGNAL OVERVIEW
This section describes the function of the System bus signals. In this section, the signals are
grouped according to function.
3.2.1.
Execution Control Signals
Table 3-1 lists the execution control signals, which control the execution and initialization of
the processor.
Pin/Signal Name
Bus Clock
Initialization
Flush
Stop Clock
Sleep
Interprocessor Communication and Interrupts
The BCLK (Bus Clock) input signal is the System bus clock. All agents drive their outputs
and latch their inputs on the BCLK rising edge. Each processor in the P6 family derives its
internal clock from BCLK by multiplying the BCLK frequency by a multiplier determined at
configuration. See Chapter 5, Configuration, for possible clock configuration frequencies.
The RESET# input signal resets all System bus agents to known states and invalidates their
internal caches. Modified or dirty cache lines are NOT written back. After RESET# is
deasserted, each processor begins execution at the power on reset vector defined during
configuration.
3-2
Table 3-1. Execution Control Signals
Pin/Signal Mnemonic
BCLK
INIT#, RESET#
FLUSH#
STPCLK#
SLP#
PICCLK, PICD[1:0]#, LINT[1:0]
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