Dual Channel Ddrcvo; Dual Channel Ddr Signal Termination And Decoupling; Dual Channel Ddrcvo Routing Guidelines; Ddrcvo Routing Guidelines - Intel Pentium M Processor Design Manual

® ®
Intel Pentium M Processor and Intel
Memory Interface Routing Guidelines
6.3.6.4

Dual Channel DDRCVO

The MCH uses a compensation signal to adjust buffer characteristics and output voltage swing over
temperature, process, and voltage skew. Calibration is done periodically by sampling the
DDRCVO_x pins on the MCH. Place the voltage divider network (see
of the MCH.
Table 40.

DDRCVO Routing Guidelines

Topology
Nominal Trace Width
Nominal Trace Spacing
Trace Length - MCH to Divider
Figure 51.

Dual Channel DDRCVO Routing Guidelines

NOTE: 'x' indicates channel A or B.
6.3.7

Dual Channel DDR Signal Termination and Decoupling

Place a 1.25 V termination plane on the top layer, just beyond (within 0.5 inch) the DIMM
connector furthest from the MCH on each channel, as shown in
must be at least 50-mils wide. Use this termination plane to terminate all DIMM signals, using one
Rtt resistor per signal. Termination may be done with individual resistors or Rpack. Decouple the
VTERM plane using one 0.1 µF decoupling capacitor per two termination resistors. Each
decoupling capacitor must have at least two vias between the top layer ground fill and the internal
ground plane. In addition place one 100 µF Tantalum capacitor on each end of the termination
island for bulk decoupling. Refer to
90
®
E7501 Chipset Platform
Parameter Intel
Resistor Divider
15 mils
20 mils
< 1.0"
MCH
®
E7501 MCH
DDR VDD
(2.5V)
49.9 Ω ± 1%
< 1"
DDRCVO_x
49.9 Ω ± 1%
Figure 52.
Figure 51) within one inch
1 nF
Figure 52. The VTERM island
Design Guide