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21.1 Reset Functions
The following two operations are available to generate the reset signal.
(1) External reset input with RESET pin
(2) Internal reset by watchdog timer overrun time detection
External reset and internal reset have no functional differences. In both cases, program execution starts at the
address at 0000H and 0001H by RESET input.
When a low level is input to the RESET pin or the watchdog timer overflows, a reset is applied and each hardware
is set to the status shown in Table 21-1. Each pin has high impedance during reset input or during oscillation
stabilization time just after reset clear.
When a high level is input to the RESET pin, the reset is cleared and program execution starts after the lapse of
oscillation stabilization time (2
reset and program execution starts after the lapse of oscillation stabilization time (2
21-4).
Cautions 1. For an external reset, input a low level for 10 µ s or more to the RESET pin.
2. During reset input, main system clock oscillation stops but subsystem clock oscillation
continues.
3. When the STOP mode is cleared by reset, the STOP mode contents are held during reset input.
However, the port pin becomes high-impedance.
RESET
Count clock
CHAPTER 21 RESET FUNCTION
17
/f
). The reset applied by watchdog timer overflow is automatically cleared after a
X
Figure 21-1. Reset Function Block Diagram
Reset controller
Watchdog timer
Stop
Preliminary User's Manual U14581EJ3V0UM00
17
/f
) (see Figures 21-2 to
X
Reset signal
Overflow
Interrupt function
271
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