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21.1 Reset Function
The following two operations are available to generate the reset signal.
(1) External reset input via RESET pin
(2) Internal reset by watchdog timer program loop time detection
External reset and internal reset have no functional differences. In both cases, program execution starts at the
address at 0000H and 0001H by RESET input. When a low level is input to the RESET pin or the watchdog timer
overflows, a reset is applied and each hardware is set to the status shown in Table 21-1. Each pin is high impedance
during reset input or during oscillation stabilization time just after reset release.
When a high level is input to the RESET pin, the reset is released and program execution starts after the lapse
of oscillation stabilization time 2
reset and program execution starts after the lapse of oscillation stabilization time 2
Cautions 1. For an external reset, input a low level for 10 µ s or more to the RESET pin.
2. During reset input, main system clock oscillation remains stopped but subsystem clock
oscillation continues.
3. When the STOP mode is released by reset, the STOP mode contents are held during reset
input. However, the port pin becomes high-impedance.
RESET
Count clock
CHAPTER 21 RESET FUNCTION
17
/f
. The reset applied by watchdog timer overflow is automatically released after
X
Figure 21-1. Reset Function Block Diagram
Reset controller
Watchdog timer
Stop
User's Manual U15798EJ2V0UD
17
/f
(see Figures 21-2 to 21-4).
X
Reset signal
Overflow
Interrupt function
415
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