Table of Contents
Advertisement
The following five operations are available to generate a reset signal.
(1) External reset input via RESET pin
(2) Internal reset by watchdog timer program loop detection
(3) Internal reset by comparison of supply voltage and detection voltage of power-on-clear (POC) circuit
(4) Internal reset by comparison of supply voltage of the low-voltage detector (LVI) or input voltage (EXLVI) from
external input pin, and detection voltage
(5) Internal reset by execution of illegal instruction
External and internal resets start program execution from the address at 0000H and 0001H when the reset signal
is generated.
A reset is effected when a low level is input to the RESET pin, the watchdog timer overflows, or by POC and LVI
circuit voltage detection or execution of illegal instruction
Tables 18-1 and 18-2. Each pin is high impedance during reset signal generation or during the oscillation stabilization
time just after a reset release, except for P130, which is low-level output.
When a low level is input to the RESET pin, the device is reset. It is released from the reset status when a high
level is input to the RESET pin and program execution is started with the internal high-speed oscillation clock after
reset processing. A reset by the watchdog timer is automatically released, and program execution starts using the
internal high-speed oscillation clock (see Figures 18-2 to 18-4) after reset processing. Reset by POC and LVI circuit
supply voltage detection is automatically released when V
execution starts using the internal high-speed oscillation clock (see CHAPTER 19 POWER-ON-CLEAR CIRCUIT
and CHAPTER 20 LOW-VOLTAGE DETECTOR) after reset processing.
Note
The illegal instruction is generated when instruction code FFH is executed.
Reset by the illegal instruction execution not issued by emulation with the in-circuit emulator or on-chip
debug emulator.
Cautions 1. For an external reset, input a low level for 10
(If an external reset is effected upon power application, the period during which the supply
voltage is outside the operating range (V
low-level input may be continued before POC is released.)
2. During reset input, the X1 clock, XT1 clock, internal high-speed oscillation clock, and internal
low-speed oscillation clock stop oscillating. External main system clock input becomes
invalid.
3. When the STOP mode is released by a reset, the RAM contents in the STOP mode are held
during reset input. However, because SFR and 2nd SFR are initialized, the port pins become
high-impedance, except for P130, which is set to low-level output.
CHAPTER 18 RESET FUNCTION
Note
Note
, and each item of hardware is set to the status shown in
DD
< 1.8 V) is not counted in the 10
DD
User's Manual U17854EJ9V0UD
≥ V
≥ V
or V
after the reset, and program
POC
DD
LVI
μ
s or more to the RESET pin.
μ
s. However, the
615
Advertisement
Table of Contents
