Table of Contents
Advertisement
Raven PCI Host Bridge & Multi-Processor Interrupt Controller Chip
Raven-Detected Errors
2
Timers
Interrupt Delivery Modes
2-62
Raven-detected errors are grouped together and sent to the interrupt logic
as a singular interrupt source. The interrupt delivery mode for this interrupt
is distributed. The Raven Error Vector-Priority Register should be
programed for high true level sensitive activation.
For system implementations where the RavenMPIC controller is not used,
the Raven-Detected Error condition will be made available by a signal
which is external to the Raven ASIC. Presumably this signal would be
connected to an externally sourced interrupt input of a MPIC controller in
a different device. Since the MPIC specification defines external I/O
interrupts to operate in the distributed mode, the delivery mode of this
error interrupt should be consistent.
There is a divide by eight pre-scaler which is synchronized to the Raven
clock (MPC processor clock). The output of the prescaler enables the
decrement of the four timers. The timers may be used for system timing or
to generate periodic interrupts. Each timer has four registers which are
used for configuration and control. They are:
Current Count Register
J
Base Count Register
J
Vector-Priority Register
J
Destination Register
J
The direct and distributed interrupt delivery modes are supported. Note
that the direct deliver mode has submodes of multicast or non-multicast.
The Interprocessor Interrupts (IPIs) and Timer interrupts operate in the
direct delivery mode. The externally sourced or I/O interrupts operate in
the distributed mode.
In the direct delivery mode, the interrupt is directed to one or both
processors. If it is directed to two processors (for example, multicast), it
will be delivered to two processors. The interrupt is delivered to the
Computer Group Literature Center Web Site
Advertisement
Table of Contents
