Table A-4: Parameters Relative To The Tx User Clock2 (Txusrclk2); Table A-5: Miscellaneous Clock Parameters - Xilinx RocketIO User Manual

Timing Parameter Tables and Diagram

Table A-4: Parameters Relative to the TX User Clock2 (TXUSRCLK2)

Parameter
Setup/Hold:
T _CFGEN/T
GCCK GCKC
T _TBYP/T
GCCK GCKC
T _TCRCE/T
GCCK GCKC
T _TPOL/T
GCCK GCKC
T _TINH/T
GCCK GCKC
T _LBK/T _LBK
GCCK GCKC
T _TRST/T
GCCK GCKC
T _TKCH/T
GCCK GCKC
T _TCDM/T
GCCK GCKC
T _TCDV/T
GCCK GCKC
T _CFGIN/T
GDCK GCKD
T _TDAT/T
GDCK GCKD
Clock to Out:
T _TBERR
GCKST
T _TKERR
GCKST
T _TRDIS
GCKDO
T _CFGOUT
GCKDO
Clock:
T
TX2PWH
T
TX2PWH

Table A-5: Miscellaneous Clock Parameters

Parameter
Clock:
T
REFPWH
T
REFPWL
T
TXPWH
T
TXPWL
Notes:
1. REFCLK is not synchronous to any RocketIO signals.
2. TXUSRCLK is not synchronous to any RocketIO signals.
UG024 (v1.5) October 16, 2002
RocketIO™ Transceiver User Guide
Function
_CFGEN Control inputs
_TBYP Control inputs
_TCRCE Control inputs
_TPOL Control inputs
_TINH Control inputs
Control inputs
_TRST Control inputs
_TKCH Control inputs
_TCDM Control inputs
_TCDV Control inputs
_CFGIN Data inputs
_TDAT Data inputs
Status outputs
Status outputs
Data outputs
Data outputs
Clock pulse width, High state TXUSRCLK2
Clock pulse width, Low state TXUSRCLK2
Function
Clock pulse width, High state REFCLK
Clock pulse width, Low state REFCLK
Clock pulse width, High state TXUSRCLK
Clock pulse width, Low state TXUSRCLK
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CONFIGENABLE
TXBYPASS8B10B[3:0]
TXFORCECRCERR
TXPOLARITY
TXINHIBIT
LOOPBACK[1:0]
TXRESET
TXCHARISK[3:0]
TXCHARDISPMODE[3:0]
TXCHARDISPVAL[3:0]
CONFIGIN
TXDATA[31:0]
TXBUFERR
TXKERR[3:0]
TXRUNDISP[3:0]
CONFIGOUT
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Signals
Signals
(1)
(1)
(2)
(2)
R
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