Register Configuration; Register Descriptions; A/D Data Registers A To D (Addra To Addrd) - Hitachi H8/3664 Hardware Manual

16.1.4

Register Configuration

Table 16.2 summarizes the A/D converter's registers.
Table 16.2 A/D Converter Registers
Address Name
H'FFFB0 A/D data register A H
H'FFFB1 A/D data register A L
H'FFFB2 A/D data register B H
H'FFFB3 A/D data register B L
H'FFFB4 A/D data register C H
H'FFFB5 A/D data register C L
H'FFFB6 A/D data register D H
H'FFFB7 A/D data register D L
H'FFFB8 A/D control/status register
H'FFFB9 A/D control register
Note: * Only 0 can be written in bit 7, to clear the flag.
16.2

Register Descriptions

16.2.1

A/D Data Registers A to D (ADDRA to ADDRD)

Bit 15
AD9
ADDRn
Initial value 0
Read/Write R
(n = A to D)
The four A/D data registers (ADDRA to ADDRD) are 16-bit read-only registers that store the
results of A/D conversion.
An A/D conversion produces 10-bit data, which is transferred for storage into the A/D data
register corresponding to the selected channel. The upper 8 bits of the result are stored in the upper
byte of the A/D data register. The lower 2 bits are stored in the lower byte. Bits 5 to 0 of an A/D
data register are reserved bits that are always read as 0. Table 16.3 indicates the pairings of analog
input channels and A/D data registers.
344
14 13 12 11
AD8 AD7 AD6 AD5
0 0 0 0
R R R R
A/D conversion data
10-bit data giving an
A/D conversion result
Abbreviation
ADDRAH
ADDRAL
ADDRBH
ADDRBL
ADDRCH
ADDRCL
ADDRDH
ADDRDL
ADCSR
ADCR
10 9 8 7
AD4 AD3 AD2 AD1
0 0 0 0
R R R R
R/W
R
R
R
R
R
R
R
R
R/(W)*
R/W
6 5 4 3
AD0 — — —
0 0 0 0
R R R R
Reserved bits
Initial Value
H'00
H'00
H'00
H'00
H'00
H'00
H'00
H'00
H'00
H'7E
2 1 0
— — —
0 0 0
R R R