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Bit 4—Reserved Bit: Bit 4 is reserved; it is always read as 1, and cannot be modified.
Bits 3 to 0—IRQ3 to IRQ0 Interrupt Enable (IEN3 to IEN0): Bits 3 to 0 enable or disable
IRQ3 to IRQ0 interrupt requests.
Bit n: IENn
0
1
3.4.4
Interrupt Flag Register 1 (IRR1)
Bit
7
IRRDT
Initial value
0
Read/Write
R/W
IRR1 is an 8-bit read/write register, in which a corresponding flag is set to 1 when a direct
transfer, a timer A, or IRQ3 to IRQ0 interrupt is requested. The flags are not cleared automatically
when an interrupt is accepted. It is necessary to write 0 to clear each flag. Upon reset, IRR1 is
initialized to H'30.
Bit 7—Direct Transfer Interrupt Request Flag (IRRDT)
Bit 7: IRRDT
0
1
Bit 6—Timer A Interrupt Request Flag (IRRTA)
Bit 6: IRRTA
0
1
56
Description
Disables interrupt requests from pin IRQn
Enables interrupt requests from pin IRQn
6
IRRTA
0
R/W
Description
Clearing conditions:
When IRRDT = 1, it is cleared by writing 0
Setting conditions:
When a direct transfer is made by executing a SLEEP instruction while DTON
= 1 in SYSCR2
Description
Clearing conditions:
When IRRTA = 1, it is cleared by writing 0
Setting conditions:
When the timer A counter value overflows from H'FF to H'00
5
4
—
—
IRRI3
1
1
—
—
3
2
IRRI2
0
0
R/W
R/W
(initial value)
(n = 3 to 0)
1
0
IRRI1
IRRI0
0
0
R/W
R/W
(initial value)
(initial value)
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