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12.5
Usage Notes
Input Pulse Width: The pulse width of the input clock signal and the input capture signal must be
at least two system clock (φ) cycles; shorter pulses will not be detected correctly.
Note on Waveform Period Setting: When compare match is selected as the TCNT clearing
source, TCNT is cleared in the last state in which the TCNT value matches GRA (when TCNT is
updated from the matching count to the next count). The actual counter frequency is therefore
given by the following formula:
φ
f =
(N + 1)
(f: counter frequency; φ: system clock frequency; N: value set in GRA)
Contention between TCNT Write and Clear: If a counter clear signal occurs in the T2 state of a
TCNT write cycle, clearing of the counter takes priority and the write is not performed. Figure
12.33 shows this timing.
φ
Address
Write signal
Counter clear
signal
TCNT
Figure 12.33 Contention between TCNT Write and Clear
228
TCNT write cycle
T1
T2
TCNT address
N
H'0000
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