Hitachi H8/3664 Hardware Manual page 414

Mnemonic
DEC.L #1, ERd
DEC.L #2, ERd
DAS.Rd
MULXU. B Rs, Rd
MULXU. W Rs, ERd
MULXS. B Rs, Rd
MULXS. W Rs, ERd
DIVXU. B Rs, Rd
DIVXU. W Rs, ERd
DIVXS. B Rs, Rd
DIVXS. W Rs, ERd
CMP.B #xx:8, Rd
CMP.B Rs, Rd
CMP.W #xx:16, Rd
CMP.W Rs, Rd
CMP.L #xx:32, ERd
CMP.L ERs, ERd
398
Operation
ERd32–1 → ERd32
L
ERd32–2 → ERd32
L
B Rd8 decimal adjust
→ Rd8
Rd8 × Rs8 → Rd16
B
(unsigned multiplication)
Rd16 × Rs16 → ERd32
W
(unsigned multiplication)
Rd8 × Rs8 → Rd16
B
(signed multiplication)
Rd16 × Rs16 → ERd32
W
(signed multiplication)
Rd16 ÷ Rs8 → Rd16
B
(RdH: remainder,
RdL: quotient)
(unsigned division)
ERd32 ÷ Rs16 → ERd32
W
(Ed: remainder,
Rd: quotient)
(unsigned division)
Rd16 ÷ Rs8 → Rd16
B
(RdH: remainder,
RdL: quotient)
(signed division)
ERd32 ÷ Rs16 → ERd32
W
(Ed: remainder,
Rd: quotient)
(signed division)
B Rd8–#xx:8
B Rd8–Rs8
W Rd16–#xx:16
W Rd16–Rs16
L ERd32–#xx:32
L ERd32–ERs32
Addressing Mode and
Instruction Length (bytes)
2
2
2
2
2
4
4
2
2
4
4
2
2
4
2
6
2
No. of
States
Condition Code
I H N Z V C
— — —
— — —
— —
* *
— — — — — —
— — — — — —
— — — —
— — — —
— — (6) (7) — —
— — (6) (7) — —
— — (8) (7) — —
— — (8) (7) — —
—
—
— (1)
— (1)
— (2)
— (2)
*1
2
2
2
14
22
16
24
14
22
16
24
2
2
4
2
4
2