Hitachi H8/3664 Hardware Manual page 14

14.8.2 Operation when a Number of Receive Errors Occur Simultaneously .................. 295
14.8.3 Break Detection and Processing............................................................................ 296
14.8.4 Mark State and Break Detection ........................................................................... 296
14.8.5 Receive Error Flags and Transmit Operation (Synchronous Mode Only)............ 296
14.8.6 Receive Data Sampling Timing and Receive Margin in Asynchronous Mode .... 296
14.8.7 Relation between RDR Reads and Bit RDRF ....................................................... 298
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Section 15 I C Bus Interface (IIC)
15.1 Overview ............................................................................................................................ 299
15.1.1 Features ................................................................................................................. 299
15.1.2 Block Diagram ...................................................................................................... 300
15.1.3 Pin Configuration .................................................................................................. 301
15.1.4 Register Configuration .......................................................................................... 302
15.2 Register Descriptions.......................................................................................................... 303
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15.2.1 I C Bus Data Register (ICDR) .............................................................................. 303
15.2.2 Slave Address Register (SAR) .............................................................................. 306
15.2.3 Second Slave Address Register (SARX) .............................................................. 307
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15.2.4 I C Bus Mode Register (ICMR)............................................................................ 307
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15.2.5 I C Bus Control Register (ICCR).......................................................................... 310
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15.2.6 I C Bus Status Register (ICSR)............................................................................. 316
15.2.7 Timer Serial Control Register (TSCR).................................................................. 320
15.3 Operation ............................................................................................................................ 321
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15.3.1 I C Bus Data Format.............................................................................................. 321
15.3.2 Master Transmit Operation ................................................................................... 322
15.3.3 Master Receive Operation ..................................................................................... 324
15.3.4 Slave Receive Operation ....................................................................................... 326
15.3.5 Slave Transmit Operation...................................................................................... 328
15.3.6 IRIC Setting Timing and SCL Control ................................................................. 330
15.3.7 Noise Canceler ...................................................................................................... 331
15.3.8 Sample Flowcharts ................................................................................................ 331
15.4 Usage Notes........................................................................................................................ 336
Section 16 A/D Converter
16.1 Overview ............................................................................................................................ 341
16.1.1 Features ................................................................................................................. 341
16.1.2 Block Diagram ...................................................................................................... 342
16.1.3 Input Pins .............................................................................................................. 343
16.1.4 Register Configuration .......................................................................................... 344
16.2 Register Descriptions.......................................................................................................... 344
16.2.1 A/D Data Registers A to D (ADDRA to ADDRD) .............................................. 344
16.2.2 A/D Control/Status Register (ADCSR) ................................................................ 345
16.2.3 A/D Control Register (ADCR).............................................................................. 347
16.3 CPU Interface ..................................................................................................................... 348
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.................................................................................................. 341