System Control Register 2 (Syscr2) - Hitachi H8/3664 Hardware Manual

Bit 3—Noise Elimination Sampling Frequency Select (NESEL): This bit selects the frequency
at which the watch clock signal (ø
relation to the oscillator clock (ø
to 10 MHz, clear NESEL to 0.
Bit 3: NESEL
0
1
Bits 2 to 0—Reserved Bits: Bits 2 to 0 are reserved: they are always read as 0 and cannot be
modified.
6.2.2

System Control Register 2 (SYSCR2)

Bit 7
SMSEL
Initial value 0
Read/Write R/W
SYSCR2 is an 8-bit read/write register for power-down mode control.
Upon reset, SYSCR2 is initialized to H'00.
Bit 7—Sleep Mode Selection (SMSEL): This bit chooses the transition to the sleep mode or
subsleep mode when the SLEEP instruction is executed. The transition after the SLEEP instruction
is executed depends on a combination of this and other control bits.
Bit 7: SMSEL
0
1
Bit 6—Low Speed on Flag (LSON): This bit chooses the system clock (ø) or subclock (ø
the CPU operating clock. The resulting operation mode after the SLEEP instruction is executed
depends on the combination of other control bits.
Bit 6: LSON
0
1
) generated by the subclock pulse generator is sampled, in
W
) generated by the system clock pulse generator. When ø
OSC
Description
Sampling rate is ø
OSC
Sampling rate is ø
OSC
6
LSON DTON
0
R/W R/W
Description
A transition is made to sleep mode.
A transition is made to subsleep mode.
Description
The CPU operates on the system clock (ø)
The CPU operates on the subclock (ø
/16
/4
5 4
MA2 MA1
0 0
R/W R/W
SUB
3 2
MA0
0 0
R/W
)
= 2
OSC
(Initial value)
1 0
SA1 SA0
0 0
R/W R/W
(Initial value)
) as
SUB
(Initial value)
83