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φ
Input capture
signal
TCNT
GRA, GRB
GRC, GRD
Figure 12.29 Buffer Operation Timing (Input Capture)
Timing of IMFA to IMFD Flag Setting at Compare Match: If a general register (GRA, GRB,
GRC, or GRD) is used as an output compare register, the corresponding IMFA, IMFB, IMFC, or
IMFD flag is set to 1 when TCNT matches the general register. The compare match signal is
generated in the last state in which the values match (when TCNT is updated from the matching
count to the next count). Therefore, when TCNT matches a general register, the compare match
signal is generated only after the next TCNT clock pulse is input. Figure 12.30 shows the timing
of the IMFA to IMFD flag setting at compare match.
φ
TCNT input
clock
TCNT
GRA to GRD
Compare
match signal
IMFA to IMFD
IRRTW
Figure 12.30 Timing of IMFA to IMFD Flag Setting at Compare Match
226
N
M
N
M
N
N
N+1
N+1
N+1
N
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