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Bits 4 and 3—Counter Clear 1 and 0 (CCLR1, CCLR0): Bits 4 and 3 specify whether or not to
clear TCNTV, and select compare match A or B or an external reset input.
When clearing is specified, if TRGE is set to 1 in TCRV1, then when TCNTV is cleared it is also
halted. Counting resumes when a trigger edge is input at the TRGV pin.
If TRGE is cleared to 0, after TCNTV is cleared it continues counting up.
Bit 4: CCLR1
Bit 3: CCLR0
0
0
1
1
0
1
Bits 2 to 0—Clock Select 2 to 0 (CKS2 to CKS0): Bits 2 to 0 and bit ICKS0 in TCRV1 select
the clock input to TCNTV.
Six internal clock sources divided from the system clock (ø) can be selected. The counter
increments on the falling edge.
If the external clock is selected, there is a further selection of incrementing on the rising edge,
falling edge, or both edges.
If TRGE is cleared to 0, after TCNTV is cleared it continues counting up.
TCRV0
Bit 2:
Bit 1:
CKS2
CKS1
0
0
1
1
0
1
174
Description
Clearing is disabled
Cleared by compare match A
Cleared by compare match B
Cleared by rising edge of external reset input
TCRV1
Bit 0:
Bit 0:
CKS0
ICKS0
0
—
1
0
1
0
0
1
1
0
1
0
—
1
—
0
—
1
—
Description
Clock input disabled
Internal clock: ø/4, falling edge
Internal clock: ø/8, falling edge
Internal clock: ø/16, falling edge
Internal clock: ø/32, falling edge
Internal clock: ø/64, falling edge
Internal clock: ø/128, falling edge
Clock input disabled
External clock: rising edge
External clock: falling edge
External clock: rising and falling edges
(Initial value)
(Initial value)
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