Hitachi H8/3664 Hardware Manual page 329

Bit 3—Acknowledge Bit Judgement Selection (ACKE): Specifies whether the value of the
acknowledge bit returned from the receiving device when using the I
and continuous transfer is performed, or transfer is to be aborted and error handling, etc.,
performed if the acknowledge bit is 1. When the ACKE bit is 0, the value of the received
acknowledge bit is not indicated by the ACKB bit, which is always 0.
Bit 3: ACKE
0
1
Bit 2—Bus Busy (BBSY): The BBSY flag can be read to check whether the I
is busy or free. In master mode, this bit is also used to issue start and stop conditions.
A high-to-low transition of SDA while SCL is high is recognized as a start condition, setting
BBSY to 1. A low-to-high transition of SDA while SCL is high is recognized as a stop condition,
clearing BBSY to 0.
To issue a start condition, use a MOV instruction to write 1 in BBSY and 0 in SCP. A retransmit
start condition is issued in the same way. To issue a stop condition, use a MOV instruction to
write 0 in BBSY and 0 in SCP. It is not possible to write to BBSY in slave mode; the I
interface must be set to master transmit mode before issuing a start condition. MST and TRS
should both be set to 1 before writing 1 in BBSY and 0 in SCP.
Bit 2: BBSY
0
1
2
Bit 1—I C Bus Interface Interrupt Request Flag (IRIC): Indicates that the I
has issued an interrupt request to the CPU. IRIC is set to 1 at the end of a data transfer, when a
slave address or general call address is detected in slave receive mode, when bus arbitration is lost
in master transmit mode, and when a stop condition is detected. IRIC is set at different times
depending on the FS bit in SAR and the WAIT bit in ICMR. See section 15.3.6, IRIC Setting
Timing and SCL Control. The conditions under which IRIC is set also differ depending on the
setting of the ACKE bit in ICCR.
IRIC is cleared by reading IRIC after it has been set to 1, then writing 0 in IRIC.
Description
The value of the acknowledge bit is ignored, and continuous transfer
is performed
If the acknowledge bit is 1, continuous transfer is interrupted
Description
Bus is free
[Clearing condition]
When a stop condition is detected
Bus is busy
[Setting condition]
When a start condition is detected
2
C bus format is to be ignored
(Initial value)
2
C bus (SCL, SDA)
2
C bus
(Initial value)
2
C bus interface
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