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Bit 1—Bit 0 Write Inhibit (B0WI): Bit 1 controls writing of data to bit 0 of timer control/status
register W.
Bit 1: B0WI
0
1
This bit is always read as 1. Data is not stored if written to this bit.
Bit 0—Watchdog Timer Reset (WRST): Bit 0 indicates that TCW has overflowed and an
internal reset signal has been generated. The internal reset signal generated by the overflow resets
the entire chip.
WRST is cleared by a reset via the RES pin or by a 0 write by software.
Bit 0: WRST
0
1
13.2.2
Timer Counter WD (TCWD)
Bit
7
TCWD7
Initial value
0
Read/Write
R/W
TCWD is an 8-bit read/write up-counter that is incremented by an input internal clock. The
TCWD value can be read or written by the CPU at any time.
When TCWD overflows (from H'FF to H'00), an internal reset signal is generated and WRST in
TCSRWD is set to 1. Upon reset, TCWD is initialized to H'00.
240
Description
Writing to bit 0 is enabled
Writing to bit 0 is disabled
Description
[Clearing conditions]
•
Reset by RES pin
•
When 0 is written to WRST while writing 0 to B0WI when TCSRWE = 1
[Setting condition]
When TCW overflows and an internal reset signal is generated
6
TCWD6
TCWD5
0
R/W
R/W
5
4
TCWD4
TCWD3
0
0
R/W
R/W
3
2
TCWD2
TCWD1
0
0
R/W
R/W
(Initial value)
(Initial value)
1
0
TCWD0
0
0
R/W
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