Timer V Operation Modes; Interrupt Sources - Hitachi H8/3664 Hardware Manual

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TCNTV Clear Timing by TMRIV: TCNTV can be cleared by a rising edge at the TMRIV pin,

as selected by bits CCLR1 and CCLR0 in TCRV0. A TMRIV input pulse width of at least 1.5

system clocks is necessary. Figure 11.8 shows the timing.

Compare match

Timer V output

Timer V Operation Modes

Table 11.3 summarizes the timer V operation states.

Table 11.3 Timer V Operation States

Operation Mode

TCRV0, TCRV1

TCORA, TCORB

Timer V has three interrupt sources: CMIA, CMIB, and OVI. Table 11.4 lists the interrupt sources

and their vector address. Each interrupt source can be enabled or disabled by an interrupt enable

bit in TCRV0. Although all three interrupts share the same vector, they have individual interrupt

flags, so software can discriminate the interrupt source.

Figure 11.8 Clear Timing by TMRIV Input