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6.7
Subactive Mode
6.7.1
Transition to the Subactive Mode
The subactive mode is entered from the sleep or subsleep mode if an interrupt is requested while
the LSON bit in SYSCR2 is set to 1. The operating frequency of the subactive mode is selected
from ø
/2, ø
/4, and ø
W
W
to the set frequency after SLEEP instruction execution. A transition to the subactive mode does
not take place if the I bit of CCR is set to 1 or the requested interrupt is disabled in the interrupt
enable register.
The subactive mode can be directly entered from the active mode. See section 6.9, Direct
Transition, for details.
6.7.2
Clearing the Subactive Mode
The subactive mode is cleared by a SLEEP instruction or by input at the RES pin.
• Clearing by SLEEP instruction
If a SLEEP instruction is executed in the subactive mode, the subactive mode is cleared and
another mode is entered. If the SSBY bit in SYSCR1 and the DTON and SMSEL bits in
SYSCR2 are cleared to 0, the sleep mode is entered; if the SSBY bit in SYSCR1, the DTON
bit in SYSCR2 are cleared to 0, and the SMSEL bit is set to 1, the subsleep mode is entered; if
the SSBY bit in SYSCR1 is set to 1 and the DTON bit in SYSCR2 is cleared to 0, the standby
mode is entered; if the DTON bit in SYSCR2 is set to 1 and the LSON bit is cleared to 0, the
active mode is directly entered. For direct transition to the active mode, see section 6.9, Direct
Transition.
• Clearing by RES pin
When the RES pin goes low, the system clock pulse generator starts. After the pulse generator
output has stabilized, the CPU starts reset exception handling if the RES pin is driven high.
Since system clock signals are supplied to the entire chip as soon as the system clock pulse
generator starts functioning, the RES pin must be kept low until the pulse generator output
stabilizes.
/8 by the SA1 and SA0 bits in SYSCR2. The operating frequency changes
W
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