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Internal Clock Switching and TCNT Operation: When the input clock is switched between
internal clocks, the TCNT may erroneously increase the count .
When an internal clock is selected, the count clock is generated by detecting the rising edges of the
internal clock obtained by dividing the system clock (φ). If the input clock is switched when the
previous clock is low and the new clock is high, the change in clock signal level (low to high) is
assumed to be a clock rising edge; a count clock pulse is generated and TCNT erroneously
increments the count. Figure 12.41 shows this timing.
Previous clock
New clock
Count clock
TCNT
Figure 12.41 Internal Clock Switching and TCNT Operation
Interrupt in Module Stop Mode: If timer W enters module stop mode while an interrupt request
is sent to the CPU, the interrupt request cannot be cleared. Before entering module stop mode,
disable interrupt requests.
236
N
N+1
The change in signal level at clock switching is
assumed to be a rising edge, and TCNT
increments the count.
N+2
N+3
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