Table of Contents
Advertisement
Contention between TCOR Write and Compare Match: If a compare match is generated in the
T
state of a TCORA or TCORB write cycle, the write to TCORA or TCORB takes precedence
3
and the compare match signal is inhibited. Figure 11.13 shows the timing.
Internal write signal
Compare match signal
Figure 11.13 Contention between TCORA Write and Compare Match
TCORA write cycle by CPU
ø
Address
TCNTV
TCORA
T
T
1
2
TCORA address
N
N
T
3
N+1
M
TCORA write data
Inhibited
187
Advertisement
Table of Contents
