Hitachi H8/3664 Hardware Manual page 68

Interrupt Source
(Reserved by
system)
Timer W
Timer V
SCI3
IIC
A/D converter
52
Interrupt
(Reserved by system)
Input capture A / compare
match A
Input capture B / compare
match B
Input capture C / compare
match C
Input capture D / compare
match D
Timer W overflow
Timer V compare match A
Timer V compare match B
Timer V overflow
SCI3 transmit end
SCI3 transmit data empty
SCI3 receive data full
SCI3 overrun error
SCI3 framing error
SCI3 parity error
Data transfer end
Address inequality
Stop conditions detected
A/D conversion end
Vector Number Vector Address
20 H'0028 to H'0029 High
21 H'002A to H'002B
22 H'002C to H'002D
23 H'002E to H'002F
24 H'0030 to H'0031
25 H'0032 to H'0033 Low
Priority