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Increment address
118
Start of erase
SWE bit ← 1
Wait 1 µs
n ← 1
Set EBR1
Enable WDT
ESU bit ← 1
Wait 100 µs
E bit ← 1
Wait 10 ms
E bit ← 0
Wait 10 µs
ESU bit ← 0
Wait 10 µs
Disable WDT
EV bit ← 1
Wait 20 µs
Verify address ← block start address
H'FF dummy write to verify address
Wait 2 µs
Read verify data
Verify data = all 1s?
Yes
No
Last address of block?
Yes
EV bit ← 0
Wait 4 µs
No
End of erasing
of all erase blocks?
Yes
SWE bit ← 0
Wait 100 µs
End of erase
Figure 7.10 Erase/Erase-Verify Flowchart
No
EV bit ← 0
Wait 4 µs
n ≤ 100?
SWE bit ← 0
Wait 100 µs
Erase failure
n ← n + 1
Yes
No
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