Hitachi H8/3664 Hardware Manual page 353

• SCL and SDA inputs are sampled in synchronization with the internal clock. The AC timing
therefore depends on the system clock cycle t
Characteristics. Note that the I
system clock frequency of less than 5 MHz.
• The I
2
C bus interface specification for the SCL rise time t
speed mode). In master mode, the I
one bit at a time during communication. If t
the time determined by the input clock of the I
extended. The SCL rise time is determined by the pull-up resistance and load capacitance of
the SCL line. To insure proper operation at the set transfer rate, adjust the pull-up resistance
and load capacitance so that the SCL rise time does not exceed the values given in the table
below.
Table 15.6 Permissible SCL Rise Time (t
t
cyc
IICX Indication
0 7.5t Normal mode
cyc
High-speed mode
1 17.5t Normal mode
cyc
High-speed mode
• The I
2
C bus interface specifications for the SCL and SDA rise and fall times are under 1000 ns
and 300 ns. The I
shown in table 15.6. However, because of the rise and fall times, the I
specifications may not be satisfied at the maximum transfer rate. Table 15.8 shows output
timing calculations for different operating frequencies, including the worst-case influence of
rise and fall times.
t fails to meet the I
BUFO
(a) to provide coding to secure the necessary interval (approximately 1 µs) between issuance of
a stop condition and issuance of a start condition, or (b) to select devices whose input timing
permits this output timing for use as slave devices connected to the I
t in high-speed mode and t
SCLLO
specifications for worst-case calculations of t
investigated include (a) adjusting the rise and fall times by means of a pull-up resistor and
capacitive load, (b) reducing the transfer rate to meet the specifications, or (c) selecting devices
whose input timing permits this output timing for use as slave devices connected to the I
bus.
2
C bus interface AC timing specifications will not be met with a
2
C bus interface monitors the SCL line and synchronizes
2
I
Specification
(Max.)
1000 ns
300 ns
1000 ns
300 ns
2
C bus interface SCL and SDA output timing is prescribed by t
2
C bus interface specifications at any frequency. The solution is either
in standard mode fail to satisfy the I
STASO
, as shown in table 17.4 in section 17, Electrical
cyc
(the time for SCL to go from low to V
sr
2
C bus interface, the high period of SCL is
) Values
sr
C Bus
ø =
5 MHz
1000 ns
300 ns
1000 ns
300 ns
/t . Possible solutions that should be
Sr Sf
is under 1000 ns (300 ns for high-
sr
Time Indication
ø = ø =
8 MHz 10 MHz
937 ns 750 ns
300 ns 300 ns
1000 ns 1000 ns
300 ns 300 ns
2
C bus interface
2
C bus.
2
C bus interface
) exceeds
IH
ø =
16 MHz
468 ns
300 ns
1000 ns
300 ns
and t , as
Scyc cyc
2
C
337