Wakeup Interrupt Flag Register (Iwpr) - Hitachi H8/3664 Hardware Manual

Bits 5 and 4—Reserved Bits: Bits 5 and 4 are reserved: they are always read as 1 and cannot be
modified.
Bit 4—Reserved Bit: Bit 4 is reserved; it is always read as 1, and cannot be modified.
Bits 3 to 0—IRQ3 to IRQ0 Interrupt Request Flags (IRRI3 to IRRI0)
Bit n: IRRIn
0
1
3.4.5

Wakeup Interrupt Flag Register (IWPR)

Bit 7
—
Initial value 1
Read/Write —
IWPR is an 8-bit read/write register, in which a corresponding flag is set to 1 when the designated
signal edge is input at pin WKP5 to WKP0. The flags are not cleared automatically when an
interrupt is accepted. It is necessary to write 0 to clear each flag. Upon reset, IWPR is initialized to
H'C0.
Bits 7 and 6— Bits 7 and 6 are reserved; they are always read as 1, and cannot be modified.
Bits 5 to 0—WKP5 to WKP0 Interrupt Request Flags (IWPF5 to IWPF0)
Bit n: IWPFn
0
1
Description
Clearing conditions:
When IRRIn = 1, it is cleared by writing 0
Setting conditions:
When pin IRQ
is designated for interrupt input and the designated signal edge
n
is input
6
— IWPF5
1
— R/W
Description
Clearing conditions:
When IWPFn = 1, it is cleared by writing 0
Setting conditions:
When pin WKPn is designated for interrupt input and the designated signal
edge is input
5 4
IWPF4 IWPF3
0 0
R/W R/W
3 2
IWPF2 IWPF1
0 0
R/W R/W
(initial value)
(n = 3 to 0)
1 0
IWPF0
0 0
R/W
(initial value)
(n = 5 to 0)
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