Hitachi H8/3664 Hardware Manual page 386

2
Table 18.4 I C Bus Interface Timing
V = 3.0 V to 5.5 V, V
CC
Item
SCL input cycle time
SCL input high width
SCL input low width
Input fall time of
SCL and SDA
SCL and SDA input
spike pulse removal
time
SDA input bus-free
time
Start condition input
hold time
Retransmission start
condition input setup
time
Setup time for stop
condition input
Data-input setup time
Data-input hold time
Capacitive load of
SCL and SDA
SCL and SDA output
fall time
Note: * The value can be changed to 17.5t
370
= 0.0 V, T = –20 to +75°C, unless otherwise specified.
SS a
Symbol Min
t 12t + 600 —
SCL cyc
t 3t + 300
SCLH cyc
t 5t + 300
SCLL cyc
t —
Sf
t —
SP
t 5t
BUF cyc
t 3t
STAH cyc
t 3t
STAS cyc
t 3t
STOS cyc
t 0.5t
SDAS cyc
t 0
SDAH
c 0
b
t —
Sf
—
cyc
Values
Typ Max
—
— —
— —
— 300
— 1t
cyc
— —
— —
— —
— —
— —
— —
— 400
— 250
— 300
, depending on the clock used in the I
Test
Unit Condition
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
pF
ns V = 4.0 V
CC
to 5.5 V
2
C module.
Reference
Figure
Figure 18.4