Timer Status Register W (Tsrw) - Hitachi H8/3664 Hardware Manual

12.2.4

Timer Status Register W (TSRW)

Bit 7
OVF
Initial value 0
Read/Write R/(W)*
Note: * Only 0 can be written, to clear the flag.
TSRW is an 8-bit read/write register that shows the TCNT overflow interrupt request and general
register (GRA, GRB, GRC, and GRD) compare match or input capture interrupt requests.
TSRW is initialized to H'70 by a reset.
Bit 7—Timer Overflow Flag (OVF): This status flag indicates the TCNT has overflowed (from
H'FFFF to H'0000). This flag is cleared by software and set by hardware; it cannot be set by
software.
Bit 7: OVF
0
1
Bits 6 to 4—Reserved: These bits cannot be modified and are always read as 1.
Bit 3—Input Capture/Compare Match Flag D (IMFD): This status flag indicates a GRD
compare match or input capture event has occurred. This flag is cleared by software and set by
hardware; it cannot be set by software.
Bit 3: IMFD
0
1
6
—
1
—
Description
[Clearing condition]
Read OVF when OVF =1, then write 0 in OVF
[Setting condition]
TCNT overflowed from H'FFFF to H'0000
Description
[Clearing condition]
Read IMFD when IMFD =1, then write 0 in IMFD
[Setting conditions]
•
TCNT = GRD when GRD functions as an output compare register
•
The TCNT value is transferred to GRD by an input capture signal when
GRD functions as an input capture register
5 4
— — IMFD
1 1
— — R/(W)*
3 2
IMFC IMFB
0 0
R/(W)* R/(W)*
1 0
IMFA
0 0
R/(W)*
(Initial value)
(Initial value)
201