Interrupts; Interrupt And Vector Address - Hitachi H8/3664 Hardware Manual

3.3

Interrupts

3.3.1

Interrupt and Vector Address

The interrupt sources that start the interrupt exception handling include 11 external interrupts and
20 internal interrupts. Table 3.2 shows the interrupts, their priorities, and their vector addresses.
When more than one interrupt is requested, handling is performed from the interrupt with the
highest priority.
NMI is the highest-priority interrupt, and cannot be masked by the I bit in CCR. All other external
interrupts excluding NMI and internal interrupts excluding address break are masked by the I bit
in CCR, and kept masked while the I bit is set to 1.
Table 3.2 Interrupt Priorities and Their Vector Addresses
Interrupt Source
RES
Watchdog timer
(Reserved by
system)
External pin
Trap instruction
executed
Address break
Sleep instruction
executed
External pin
Timer A
Interrupt
Reset
(Reserved by system)
NMI
Trap instruction #0
Trap instruction #1
Trap instruction #2
Trap instruction #3
Break conditions satisfied
Transferred directly
IRQ0
IRQ1
IRQ2
IRQ3
WKP5
Timer A overflow
Vector Number Vector Address
0 H'0000 to H'0001 High
1 H'0002 to H'0003
2 H'0004 to H'0005
3 H'0006 to H'0007
4 H'0008 to H'0009
5 H'000A to H'000B
6 H'000C to H'000D
7 H'000E to H'000F
8 H'0010 to H'0011
9 H'0012 to H'0013
10 H'0014 to H'0015
11 H'0016 to H'0017
12 H'0018 to H'0019
13 H'001A to H'001B
14 H'001C to H'001D
15 H'001E to H'001F
16 H'0020 to H'0021
17 H'0022 to H'0023
18 H'0024 to H'0025
19 H'0026 to H'0027 Low
Priority
51