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Bit 2—Slave Address Recognition Flag (AAS): In I
set to 1 if the first frame following a start condition matches bits SVA6 to SVA0 in SAR, or if the
general call address (H'00) is detected.
AAS is cleared by reading AAS after it has been set to 1, then writing 0 in AAS. In addition, AAS
is reset automatically by write access to ICDR in transmit mode, or read access to ICDR in receive
mode.
Bit 2: AAS
0
1
Bit 1—General Call Address Recognition Flag (ADZ): In I
this flag is set to 1 if the first frame following a start condition is the general call address (H'00).
ADZ is cleared by reading ADZ after it has been set to 1, then writing 0 in ADZ. In addition, ADZ
is reset automatically by write access to ICDR in transmit mode, or read access to ICDR in receive
mode.
Bit 1: ADZ
0
1
Description
[Clearing conditions]
1. When ICDR data is written (transmit mode) or read (receive mode)
2. When 0 is written in AAS after reading AAS = 1
3. In master mode
[Setting condition]
When the slave address or general call address is detected in slave receive
mode and FS = 0
Description
[Clearing conditions]
1. When ICDR data is written (transmit mode) or read (receive mode)
2. When 0 is written in ADZ after reading ADZ = 1
3. In master mode
[Setting condition]
When the general call address is detected in slave receive mode and (FSX = 0
or FS = 0)
2
C bus format slave receive mode, this flag is
2
C bus format slave receive mode,
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