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Figure 12.25 shows the output compare timing.
φ
TCNT input
clock
TCNT
GRA to GRD
Compare
match signal
FTIOA to FTIOD
Input Capture Timing: Input capture on the rising edge, falling edge, or both edges can be
selected through settings in TIOR0 and TIOR1. Figure 12.26 shows the timing when the falling
edge is selected. The pulse width of the input capture signal must be at least two system clock (φ)
cycles; shorter pulses will not be detected correctly.
ø
Input capture
input
Input capture
signal
TCNT
GRA to GRD
224
N
N
Figure 12.25 Output Compare Timing
N–1
N
Figure 12.26 Input Capture Timing
N+1
N+1
N+2
N
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