Table of Contents
Advertisement
Bit 3—Reserved: This bit cannot be modified and is always read as 1.
Bit 2—PWM Mode D (PWMD): Selects whether the compare match output pin (FTIOD)
operates normally or in PWM mode.
Bit 2: PWMD
0
1
Note: * The period is specified in GRA.
Bit 1—PWM Mode C (PWMC): Selects whether the compare match output pin (FTIOC)
operates normally or in PWM mode.
Bit 1: PWMC
0
1
Note: * The period is specified in GRA.
Bit 0—PWM Mode B (PWMB): Selects whether the compare match output pin (FTIOB)
operates normally or in PWM mode.
Bit 0: PWMB
0
1
Note: * The period is specified in GRA.
12.2.2
Timer Control Register W (TCRW)
Bit
7
CCLR
Initial value
0
Read/Write
R/W
TCRW is an 8-bit read/write register that specifies the timer output levels, selects the timer
counter clock source, and selects how the counter is cleared.
TCRW is initialized to H'00 by a reset.
Description
FTIOD operates normally (output compare output)
FTIOD operates in PWM mode*
Description
FTIOC operates normally (output compare output)
FTIOC operates in PWM mode*
Description
FTIOB operates normally (output compare output)
FTIOB operates in PWM mode*
6
CKS2
CKS1
0
R/W
R/W
5
4
CKS0
TOD
0
0
R/W
R/W
3
2
TOC
TOB
0
0
R/W
R/W
(Initial value)
(Initial value)
(Initial value)
1
0
TOA
0
0
R/W
197
Advertisement
Table of Contents
