Hitachi H8/3660 Manuals

Manuals and User Guides for Hitachi H8/3660. We have 1 Hitachi H8/3660 manual available for free PDF download: Hardware Manual

Hitachi H8/3660 Hardware Manual (463 pages)

Brand: Hitachi | Category: Computer Hardware | Size: 1.45 MB

Table of Contents
7
Section 1 Overview
17
Features
17
Internal Block Diagram
20
Pin Arrangement
21
Pin Functions
23
Section 2 CPU
27
Features
27
Address Space and Memory Map
28
Register Configuration
31
- General Registers
  32
- Program Counter (PC)
  33
- Condition Code Register (CCR)
  33
Data Formats
35
- General Register Data Formats
  35
- Memory Data Formats
  37
Instruction Set
38
- Instruction Set Overview
  38
- Basic Instruction Formats
  48
Addressing Modes and Effective Address Calculation
49
- Addressing Modes
  49
- Effective Address Calculation
  51
Basic Bus Cycle
55
- Access to On-Chip Memory (RAM, ROM)
  55
- Access to On-Chip Peripheral Modules
  56
CPU States
57
- Overview
  57
Application Notes
58
Section 3 Exception Handling
65
Overview
65
- Exception Handling Types
  65
Reset
65
- Reset Sequence
  65
- Reset by Watchdog Timer
  66
- Interrupt Immediately after Reset
  66
Interrupts
67
- Interrupt and Vector Address
  67
Interrupt Control Registers
69
Interrupt Sources
74
- External Interrupts
  74
- Internal Interrupts
  74
- Interrupt Operations
  75
- Interrupt Response Time
  78
Trap Instruction
78
Application Notes
78
- Notes on Stack Area Use
  78
- Notes on Rewriting Port Mode Registers
  79
Section 4 Address Break
83
Overview
83
- Block Diagram
  83
- Register Configuration
  84
Register Descriptions
84
Operation
88
Section 5 Clock Pulse Generators
91
Overview
91
- Block Diagram
  91
- System Clock and Subclock
  91
System Clock Generator
92
Subclock Generator
94
Prescalers
95
Usage Notes
96
- Note on Oscillators
  96
- Notes on Board Design
  96
Section 6 Power-Down Modes
97
Overview
97
- Register Configuration
  97
Register Descriptions
98
Mode Transition Conditions
103
Sleep Mode
106
- Transition to the Sleep Mode
  106
Standby Mode
106
Subsleep Mode
108
- Transition to the Subsleep Mode
  108
- Clearing the Subsleep Mode
  108
Subactive Mode
109
- Transition to the Subactive Mode
  109
- Clearing the Subactive Mode
  109
Active Mode
110
Direct Transition
111
- Direct Transition Time
  111
Module Standby Mode
112
Section 7 ROM
113
Features
113
Overview
114
- Block Diagram
  114
- On-Board Programming Mode
  115
- Block Configuration
  119
- Pin Configuration
  119
- Register Configuration
  120
Register Descriptions
120
Boot Mode
125
- Automatic SCI Bit Rate Adjustment
  127
- Programming Control Program Area
  127
- Notes on Use of Boot Mode
  128
User Program Mode
128
Programming/Erasing Flash Memory
129
- Program/Program-Verify
  130
- Erase/Erase-Verify
  133
- Interrupts During Flash Memory Programming/Erasing
  133
Protection
135
- Hardware Protection
  135
- Software Protection
  136
- Error Protection
  136
Interrupt Handling When Programming/Erasing Flash Memory
137
Flash Memory and Power-Down States
138
Flash Memory Programmer Mode
138
- Socket Adapter Pin Correspondence Diagram
  139
- Programmer Mode Operation
  141
- Memory Read Mode
  142
- Auto-Program Mode
  145
- Auto-Erase Mode
  147
- Status Read Mode
  149
- Status Polling
  150
- Programmer Mode Transition Time
  150
- Notes on Memory Programming
  151
Section 8 RAM
153
Overview
153
- Block Diagram
  153
Section 9 I/O Ports
155
Overview
155
Port 1
156
- Overview
  156
- Register Configuration and Description
  156
- Port Data Register 1 (PDR1)
  157
- Port Control Register 1 (PCR1)
  157
- Port Pull-Up Control Register 1 (PUCR1)
  157
- Port Mode Register 1 (PMR1)
  158
- Pin Functions
  160
- MOS Input Pull-Up
  161
Port 2
162
- Overview
  162
- Register Configuration and Description
  162
- Port Data Register 2 (PDR2)
  162
- Port Control Register 2 (PCR2)
  163
- Pin Functions
  164
Port 5
165
- Overview
  165
- Register Configuration and Description
  165
- Port Data Register 5 (PDR5)
  166
- Port Control Register 5 (PCR5)
  166
- Port Pull-Up Control Register 5 (PUCR5)
  167
- Port Mode Register 5 (PMR5)
  167
- Pin Functions
  168
- MOS Input Pull-Up
  169
Port 7
170
- Overview
  170
- Register Configuration and Description
  170
- Port Data Register 7 (PDR7)
  170
- Port Control Register 7 (PCR7)
  171
- Pin Functions
  171
Port 8
172
- Overview
  172
- Register Configuration and Description
  172
- Port Data Register 8 (PDR8)
  173
- Port Control Register 8 (PCR8)
  173
- Pin Functions
  174
Port B
177
- Overview
  177
- Register Configuration and Description
  177
- Port Data Register B (PDRB)
  177
- Pin Functions
  178
Section 10 Timer a
179
Overview
179
- Features
  179
- Block Diagram
  180
- Pin Configuration
  180
- Register Configuration
  181
Register Descriptions
181
- Timer Mode Register a (TMA)
  181
- Timer Counter a (TCA)
  182
Timer Operation
183
- Interval Timer Operation
  183
- Clock Time Base Operation
  183
- Clock Output
  183
Timer a Operation States
184
Section 11 Timer V
185
Overview
185
- Features
  185
- Block Diagram
  186
- Pin Configuration
  187
- Register Configuration
  187
Register Descriptions
188
Timer Operation
194
- Timer V Operation Modes
  198
- Interrupt Sources
  198
- Application Examples
  199
- Application Notes
  201
Section 12 Timer W
207
Overview
207
- Features
  207
- Block Diagrams
  209
- Input/Output Pins
  210
- Register Configuration
  211
Register Description
212
- Timer Mode Register W (TMRW)
  212
- Timer Control Register W (TCRW)
  213
- Timer Interrupt Enable Register W (TIERW)
  215
- Timer Status Register W (TSRW)
  217
- Timer I/O Control Register 0 (TIOR0)
  219
- Timer I/O Control Register 1 (TIOR1)
  220
- Timer Counter (TCNT)
  222
- General Registers a to D (GRA to GRD)
  222
CPU Interface
223
- 16-Bit Registers
  223
Operation
224
- Overview
  224
- Operation Timing
  239
Usage Notes
244
Section 13 Watchdog Timer
253
Overview
253
- Features
  253
- Block Diagram
  253
- Register Configuration
  254
Register Descriptions
254
Operation
258
- Watchdog Timer Operating Modes
  259
Section 14 Serial Communication Interface 3
261
Overview
261
- Features
  261
- Block Diagram
  263
- Pin Configuration
  264
- Register Configuration
  264
Register Descriptions
265
- Receive Shift Register (RSR)
  265
- Receive Data Register (RDR)
  265
- Transmit Shift Register (TSR)
  266
- Transmit Data Register (TDR)
  266
- Serial Mode Register (SMR)
  267
- Serial Control Register 3 (SCR3)
  269
- Serial Status Register (SSR)
  272
- Bit Rate Register (BRR)
  276
Operation
283
- Asynchronous Mode
  283
- Synchronous Mode
  283
- Interrupts and Continuous Transmission/Reception
  285
Operation in Asynchronous Mode
287
- Data Transfer Format
  287
- Clock
  289
- Data Transfer Operations
  289
Operation in Synchronous Mode
296
- Data Transfer Format
  297
- Clock
  297
- Data Transfer Operations
  298
Multiprocessor Communication Function
303
Interrupts
310
Usage Notes
311
Section 15 I C Bus Interface (IIC)
315
Overview
315
- Features
  315
- Block Diagram
  316
- Pin Configuration
  317
- Register Configuration
  318
Register Descriptions
319
- I 2 C Bus Data Register (ICDR)
  319
- Slave Address Register (SAR)
  322
- Second Slave Address Register (SARX)
  323
- I 2 C Bus Mode Register (ICMR)
  323
- I 2 C Bus Control Register (ICCR)
  326
- I 2 C Bus Status Register (ICSR)
  332
- Timer Serial Control Register (TSCR)
  336
Operation
337
- C Bus Data Format
  337
- Master Transmit Operation
  338
- Master Receive Operation
  340
- Slave Receive Operation
  342
- Slave Transmit Operation
  344
- IRIC Setting Timing and SCL Control
  346
- Noise Canceler
  347
- Sample Flowcharts
  347
Usage Notes
352
Section 16 A/D Converter
357
Overview
357
- Features
  357
- Block Diagram
  358
- Input Pins
  359
- Register Configuration
  360
Register Descriptions
360
CPU Interface
364
Operation
366
- Single Mode (SCAN = 0)
  366
- Scan Mode (SCAN = 1)
  368
- Input Sampling and A/D Conversion Time
  370
- External Trigger Input Timing
  371
Interrupts
372
Usage Notes
372
Section 17 Power Supply Circuit
375
Overview
375
When Using the Internal Power Supply Step-Down Circuit
375
When Not Using the Internal Power Supply Step-Down Circuit
376
Section 18 Electrical Characteristics
377
Absolute Maximum Ratings
377
Electrical Characteristics (F-ZTAT™ Version)
377
- Power Supply Voltage and Operating Ranges
  377
- DC Characteristics
  379
- AC Characteristics
  384
- A/D Converter Characteristics
  388
- Watchdog Timer
  389
- Flash Memory Characteristics (Preliminary)
  390
Electrical Characteristics (Mask ROM Version)
392
- Power Supply Voltage and Operating Ranges
  392
- DC Characteristics
  394
- AC Characteristics
  399
- A/D Converter Characteristics
  403
- Watchdog Timer
  404
Operation Timing
405
Output Load Circuit
408
Appendix A Instruction Set
409
Instruction List
409
- Data Transfer Instructions
  411
- Arithmetic Instructions
  413
- Bit Manipulation Instructions
  418
Operation Code Map
424
Number of Execution States
427
Combinations of Instructions and Addressing Modes
434
Appendix B Internal I/O Registers
435
Register Addresses
435
B.2 Register Bits
438
Register Bits
438
Appendix C I/O Port Block Diagrams
441

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