Break Data Registers (Bdrh, Bdrl); Operation - Hitachi H8/3664 Hardware Manual

4.2.4

Break Data Registers (BDRH, BDRL)

Bit 7
BDRH7
Initial value
Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined
Read/Write R/W
Bit 7
BDRL7
Initial value
Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined
Read/Write R/W
BDR (BDRH, BDRL) is a 16-bit read/write register that sets the data for generating an address
break interrupt. BDRH is compared with the upper 8-bit data bus. BDRL is compared with the
lower 8-bit data bus. When memory or registers are accessed by byte, the upper 8-bit data bus is
used for even and odd addresses in the data transmission. Therefore, comparison data must be set
in BDRH for byte access. For word access, the data bus used depends on the address. See section
4.2.1, Address Break Control Register, for details.
4.3

Operation

When the ABIE bit in ABRKSR is set to 1, if the ABIF bit in ABRKSR is set to 1 by the
combination of the address set in BAR, the data set in BDR, and the conditions set in ABRKCR,
the address break function generates an interrupt request to the CPU. When the interrupt request
is accepted, interrupt exception handling starts after the instruction being executed ends. The
address break interrupt is not masked because of the I bit in CCR of the CPU.
72
6 5
BDRH6 BDRH5
R/W R/W
6 5
BDRL6 BDRL5
R/W R/W
4 3
BDRH4 BDRH3
R/W R/W
4 3
BDRL4 BDRL3
R/W R/W
2 1
BDRH2 BDRH1
R/W R/W
2 1
BDRL2 BDRL1
R/W R/W
0
BDRH0
R/W
0
BDRL0
R/W