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[5] When one frame of data has been received, the IRIC flag in ICCR and the IRTR flag in
ICSR are set to 1 at the rise of the 9th receive clock pulse. The master device outputs SCL
clock to receive next data.
[6] Read ICDR.
[7] Clear the IRIC flag to detect next wait operation. Data reception process from [5] to [7]
should be executed during one byte reception period after IRIC flag clearing in [4] or [9] to
release wait status.
[8] The IRIC flags set to 1 at the fall of 8th receive clock pulse. SCL is automatically fixed low
in synchronization with the internal clock until the IRIC flag clearing. If this frame is the last
receive data, execute step [10] to halt reception.
[9] Clear the IRIC flag in ICCR to cancel wait operation. The master device outputs the 9th
clock and drives SDA at the 9th receive clock pulse to return an ackowledge signal. Data can
be received continuously by repeating step [5] to [9].
[10] Set the ACKB bit in ICSR to 1 so as to return "No acknowledge" data. Also set the TRS bit
to 1 to switch from receive mode to transmit mode.
[11] Clear IRIC flag to 0 to release from the Wait State.
[12] When one frame of data has been received, the IRIC flag is set to 1 at the rise of the 9th
receive clock pulse.
[13] Clear the WAIT bit to 0 to switch from wait mode to no wait mode. Read ICDR and the
IRIC flag to 0. Clearing of the IRIC flag should be after the WAIT = 0.
[14] Clear the BBSY bit and SCP bit to 0. This changes SDA from low to high when SCL is high,
and generates the stop condition.
Master tansmit mode
SCL
(master output)
9
SDA
A
(slave output)
SDA
(master output)
IRIC
IRTR
ICDR
User processing
[1] TRS cleared to 0
WAIT set to 1
ACKB cleared to 0
Figure 15.7 Example of Master Receive Mode Operation Timing (1)
Master receive mode
1
2
3
Bit 7
Bit 6
Bit 5
Bit 4
Data 1
[2] ICDR read
[2] IRIC clearance
(dummy read)
(NLS = ACKB = 0, WAIT = 1)
4
5
6
7
8
Bit 3
Bit 2
Bit 1
Bit 0
[3]
[4] IRIC clearance
9
1
2
3
Bit 7
Bit 6
Bit 5
Data 2
[5]
A
Data 1
[7] IRIC clearance
[6] ICDR read
(Data 1)
4
5
Bit 4
Bit 3
325
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