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Contention between General Register Write and Input Capture: If a capturing signal is
generated in the T2 state of a general register write cycle, writing to GR takes priority and input
capture (data transfer from TCNT to GR) is not performed. Figure 12.38 shows this timing.
φ
Address
Write signal
Input capture
signal
GR
TCNT
Figure 12.38 Contention between General Register Write and Input Capture
GR write cycle
T1
T2
GR address
N
M (GR write data)
X
X+1
233
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