Hitachi H8/3664 Hardware Manual page 345

slave device sequentially sends the data written into ICDR in accordance with the clock output
by the master device at the timing shown in figure 15.10.
[4] When one frame of data has been transmitted, the IRIC flag in ICCR is set to 1 at the rise of
the 9th transmit clock pulse. If the TDRE internal flag has been set to 1, this slave device
drives SCL low from the fall of the transmit clock until data is written to ICDR. The master
device drives SDA low at the 9th clock pulse, and returns an acknowledge signal. As this
acknowledge signal is stored in the ACKB bit in ICSR, this bit can be used to determine
whether the transfer operation was performed normally. When the TDRE internal flag is 0, the
data written into ICDR is transferred to ICDRS, transmission is started, and the TDRE internal
flag and the IRIC and IRTR flags are set to 1 again.
[5] To continue transmission, clear the IRIC flag to 0, then write the next data to be transmitted
into ICDR. The TDRE flag is cleared to 0.
Transmit operations can be performed continuously by repeating steps [4] and [5]. To end
transmission, write H'FF to ICDR. When SDA is changed from low to high when SCL is high,
and the stop condition is detected, the BBSY flag in ICCR is cleared to 0.
Slave receive mode
SCL
(master output)
8
SCL
(slave output)
SDA
(slave output)
SDA
(master output)
R/W
TDRE
IRIC
ICDRT
ICDRS
[3] IRIC
User processing
clearance
Figure 15.10 Example of Slave Transmit Mode Operation Timing
Slave transmit mode
9 1 2
Bit 7 Bit 6
A
[2]
Interrupt Interrupt
request request
generation generation
Data 1
Data 1
[3] ICDR
write
3 4 5 6
Bit 5 Bit 4 Bit 3 Bit 2
Data 1
Data 2
[3] ICDR
write
(MLS = 0)
7 8 9 1
Bit 1 Bit 0 Bit 7
A
[3]
Interrupt
request
generation
Data 2
[5] IRIC [5] ICDR
clearance write
2
Bit 6
Data 2
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