Hitachi H8/3664 Hardware Manual page 246

Contention between General Register Write and Compare Match in Buffer Operation: If a
compare match occurs in the T2 state of a general register write cycle, writing takes priority and
the buffer operation (data transfer from the buffer register to the general register) is not performed.
Figure 12.35 shows this timing.
φ
Address
Write signal
Compare
match signal
GR
Buffer register
Figure 12.35 Contention between General Register Write and Compare Match
230
GR write cycle
T1 T2
GR address
N M (GR write data)
X
in Buffer Operation