Table of Contents
Advertisement
7.4.3
Notes on Use of Boot Mode.................................................................................. 112
7.5
User Program Mode ........................................................................................................... 112
7.6
Programming/Erasing Flash Memory ................................................................................ 113
7.6.1
Program/Program-Verify ...................................................................................... 114
7.6.2
Erase/Erase-Verify ................................................................................................ 117
7.6.3
Interrupts during Flash Memory Programming/Erasing ....................................... 117
7.7
Protection............................................................................................................................ 119
7.7.1
Hardware Protection.............................................................................................. 119
7.7.2
Software Protection ............................................................................................... 120
7.7.3
Error Protection ..................................................................................................... 120
7.8
Interrupt Handling when Programming/Erasing Flash Memory........................................ 121
7.9
Flash Memory and Power-Down States ............................................................................. 122
7.10 Flash Memory Programmer Mode ..................................................................................... 122
7.10.1 Socket Adapter Pin Correspondence Diagram...................................................... 123
7.10.2 Programmer Mode Operation................................................................................ 125
7.10.3 Memory Read Mode.............................................................................................. 126
7.10.4 Auto-Program Mode ............................................................................................. 129
7.10.5 Auto-Erase Mode .................................................................................................. 131
7.10.6 Status Read Mode.................................................................................................. 133
7.10.7 Status Polling ........................................................................................................ 134
7.10.8 Programmer Mode Transition Time...................................................................... 134
7.10.9 Notes on Memory Programming........................................................................... 135
Section 8
8.1
Overview ............................................................................................................................ 137
8.1.1
Block Diagram ...................................................................................................... 137
Section 9
9.1
Overview ............................................................................................................................ 139
9.2
Port 1 .................................................................................................................................. 140
9.2.1
Overview ............................................................................................................... 140
9.2.2
Register Configuration and Description................................................................ 140
9.2.3
Port Data Register 1 (PDR1) ................................................................................. 141
9.2.4
Port Control Register 1 (PCR1) ............................................................................ 141
9.2.5
Port Pull-Up Control Register 1 (PUCR1)............................................................ 141
9.2.6
Port Mode Register 1 (PMR1) .............................................................................. 142
9.2.7
Pin Functions......................................................................................................... 144
9.2.8
MOS Input Pull-Up ............................................................................................... 145
9.3
Port 2 .................................................................................................................................. 146
9.3.1
Overview ............................................................................................................... 146
9.3.2
Register Configuration and Description................................................................ 146
9.3.3
Port Data Register 2 (PDR2) ................................................................................. 146
9.3.4
Port Control Register 2 (PCR2) ............................................................................ 147
iv
.................................................................................................................... 137
............................................................................................................. 139
Advertisement
Table of Contents
